R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Write to LCA
Read Status
RS, CS0
WS/CS0
RS, CS1
WS, CS1
1
T
CA
3
T
4
7
CD
2
T
DC
READY
BUSY
D7
D0-D7
CCLK
4
T
WTRB
6
T
BUSY
RDY/BUSY
DOUT
Previous Byte D6
D7
D0
D1
D2
X6097
Description
Effective Write time
Symbol
TCA
Min
Max
Units
6
1
100
ns
(CS0, WS=Low; RS, CS1=High)
Write
RDY
DIN setup time
2
3
4
TDC
TCD
60
0
ns
ns
ns
DIN hold time
RDY/BUSY delay after end of
Write or Read
TWTRB
60
60
9
RDY/BUSY active after beginning
of Read
7
6
ns
RDY/BUSY Low output (Note 4)
TBUSY
2
CCLK
periods
Notes: 1. Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High.
2. The time from the end of WS to CCLK cycle for the new byte of data depends on the completion of previous byte
processing and the phase of the internal timing generator for CCLK.
3. CCLK and DOUT timing is tested in slave mode.
4. T
T
indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest
BUSY
occurs when a byte is loaded into an empty parallel-to-serial converter. The longest T
occurs when a new word
BUSY
BUSY
is loaded into the input register before the second-level buffer has started shifting out data
This timing diagram shows very relaxed requirements. Data need not be held beyond the rising edge of WS. RDY/BUSY will
go active within 60 ns after the end of WS. A new write may be asserted immediately after RDY/BUSY goes Low, but write
may not be terminated until RDY/BUSY has been High for one CCLK period.
Figure 59: Asynchronous Peripheral Mode Programming Switching Characteristics
May 14, 1999 (Version 1.6)
6-67
XILINX [ XILINX, INC ]
