欢迎访问ic37.com |
会员登录 免费注册
发布采购

5962-9473002MXC 参数 Datasheet PDF下载

5962-9473002MXC图片预览
型号: 5962-9473002MXC
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 576 CLBs, 10000 Gates, 90.9MHz, 1368-Cell, CMOS, CPGA223, CERAMIC, PGA-223]
分类和应用: 时钟可编程逻辑
文件页数/大小: 68 页 / 685 K
品牌: XILINX [ XILINX, INC ]
 浏览型号5962-9473002MXC的Datasheet PDF文件第51页浏览型号5962-9473002MXC的Datasheet PDF文件第52页浏览型号5962-9473002MXC的Datasheet PDF文件第53页浏览型号5962-9473002MXC的Datasheet PDF文件第54页浏览型号5962-9473002MXC的Datasheet PDF文件第56页浏览型号5962-9473002MXC的Datasheet PDF文件第57页浏览型号5962-9473002MXC的Datasheet PDF文件第58页浏览型号5962-9473002MXC的Datasheet PDF文件第59页  
R
XC4000E and XC4000X Series Field Programmable Gate Arrays  
Table 23: Pin Functions During Configuration  
CONFIGURATION MODE <M2:M1:M0>  
SLAVE  
SERIAL  
<1:1:1>  
M2(HIGH) (I)  
M1(HIGH) (I)  
M0(HIGH) (I)  
HDC (HIGH)  
LDC (LOW)  
INIT  
MASTER  
SERIAL  
<0:0:0>  
M2(LOW) (I)  
M1(LOW) (I)  
M0(LOW) (I)  
HDC (HIGH)  
LDC (LOW)  
INIT  
SYNCH.  
PERIPHERAL  
<0:1:1>  
M2(LOW) (I)  
M1(HIGH) (I)  
M0(HIGH) (I)  
HDC (HIGH)  
LDC (LOW)  
INIT  
ASYNCH.  
MASTER  
MASTER  
USER  
OPERATION  
PERIPHERAL PARALLEL DOWN PARALLEL UP  
<1:0:1>  
M2(HIGH) (I)  
M1(LOW) (I)  
M0(HIGH) (I)  
HDC (HIGH)  
LDC (LOW)  
INIT  
<1:1:0>  
M2(HIGH) (I)  
M1(HIGH) (I)  
M0(LOW) (I)  
HDC (HIGH)  
LDC (LOW)  
INIT  
<1:0:0>  
M2(HIGH) (I)  
M1(LOW) (I)  
M0(LOW) (I)  
HDC (HIGH)  
LDC (LOW)  
INIT  
(I)  
(O)  
(I)  
I/O  
I/O  
I/O  
DONE  
DONE  
DONE  
DONE  
DONE  
DONE  
DONE  
PROGRAM (I)  
CCLK (I)  
PROGRAM (I)  
CCLK (O)  
PROGRAM (I)  
CCLK (I)  
RDY/BUSY (O)  
PROGRAM (I)  
CCLK (O)  
RDY/BUSY (O)  
RS (I)  
PROGRAM (I)  
CCLK (O)  
RCLK (O)  
PROGRAM (I)  
CCLK (O)  
RCLK (O)  
PROGRAM  
CCLK (I)  
I/O  
I/O  
CS0 (I)  
I/O  
DATA 7 (I)  
DATA 6 (I)  
DATA 5 (I)  
DATA 4 (I)  
DATA 3 (I)  
DATA 2 (I)  
DATA 1 (I)  
DATA 0 (I)  
DOUT  
DATA 7 (I)  
DATA 6 (I)  
DATA 5 (I)  
DATA 4 (I)  
DATA 3 (I)  
DATA 2 (I)  
DATA 1 (I)  
DATA 0 (I)  
DOUT  
DATA 7 (I)  
DATA 6 (I)  
DATA 5 (I)  
DATA 4 (I)  
DATA 3 (I)  
DATA 2 (I)  
DATA 1 (I)  
DATA 0 (I)  
DOUT  
TDI  
DATA 7 (I)  
DATA 6 (I)  
DATA 5 (I)  
DATA 4 (I)  
DATA 3 (I)  
DATA 2 (I)  
DATA 1 (I)  
DATA 0 (I)  
DOUT  
TDI  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
6
DIN (I)  
DOUT  
TDI  
DIN (I)  
DOUT  
TDI  
SGCK4-GCK5-I/O  
TDI  
TDI  
TDI-I/O  
TCK  
TCK  
TCK  
TCK  
TCK  
TCK  
TCK-I/O  
TMS  
TDO  
TMS  
TDO  
TMS  
TDO  
TMS  
TDO  
TMS  
TDO  
TMS  
TDO  
TMS-I/O  
TDO-(O)  
WS (I)  
A0  
A0  
I/O  
A1  
A1  
PGCK4-GCK6-I/O  
CS1  
A2  
A2  
I/O  
A3  
A3  
I/O  
A4  
A4  
I/O  
A5  
A5  
I/O  
A6  
A6  
I/O  
A7  
A7  
I/O  
A8  
A8  
I/O  
A9  
A9  
I/O  
A10  
A10  
I/O  
A11  
A11  
I/O  
A12  
A12  
I/O  
A13  
A13  
I/O  
A14  
A14  
I/O  
A15  
A15  
SGCK1-GCK7-I/O  
A16  
A16  
PGCK1-GCK8-I/O  
A17  
A17  
I/O  
A18*  
A18*  
I/O  
A19*  
A20*  
A19*  
A20*  
I/O  
I/O  
A21*  
A21*  
I/O  
ALL OTHERS  
* XC4000X only  
Notes 1. A shaded table cell represents a 50 k- 100 kpull-up before and during configuration.  
2. (I) represents an input; (O) represents an output.  
3. INIT is an open-drain output during configuration.  
May 14, 1999 (Version 1.6)  
6-59  
 复制成功!