R
XC4000E and XC4000X Series Field Programmable Gate Arrays
4
C
• • • C
1
4
EC
D
WE
D
1
0
D
IN
Enable
WRITE
DECODER
16-LATCH
ARRAY
G'
MUX
4
G
• • • G
4
1
1 of 16
4
READ ADDRESS
D
IN
Enable
WRITE
DECODER
16-LATCH
ARRAY
F'
MUX
4
F
• • • F
4
1
1 of 16
4
READ ADDRESS
X6746
6
Figure 9: 16x2 (or 16x1) Level-Sensitive Single-Port RAM
4
C
• • • C
1
4
EC
D /A
D
0
WE
1
4
D
IN
Enable
WRITE
DECODER
16-LATCH
ARRAY
G'
MUX
G
F
• • • G
• • • F
4
1
1
4
4
1 of 16
4
READ ADDRESS
H'
D
IN
Enable
WRITE
DECODER
16-LATCH
ARRAY
F'
MUX
4
1 of 16
4
READ ADDRESS
X6749
Figure 10: 32x1 Level-Sensitive Single-Port RAM (F and G addresses are identical)
May 14, 1999 (Version 1.6)
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