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X1243S8T1 参数 Datasheet PDF下载

X1243S8T1图片预览
型号: X1243S8T1
PDF下载: 下载PDF文件 查看货源
内容描述: [Real Time Clock, 0 Timer(s), CMOS, PDSO8, PLASTIC, SOIC-8]
分类和应用: 时钟光电二极管外围集成电路
文件页数/大小: 18 页 / 285 K
品牌: XICOR [ XICOR INC. ]
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X1243 – Preliminary Information  
Figure 5. Acknowledge Response From Receiver  
SCL from  
Master  
1
8
9
Data Output  
from Transmitter  
Data Output  
from Receiver  
Start  
Acknowledge  
Acknowledge  
WRITE OPERATIONS  
Byte Write  
Acknowledge is a software convention used to indicate  
successful data transfer. The transmitting device, either  
master or slave, will release the bus after transmitting  
eight bits. During the ninth clock cycle, the receiver will  
pull the SDA line LOW to acknowledge that it received  
the eight bits of data. Refer to Figure 5.  
For a byte write operation (Refer to Figure 13), the  
device requires the Slave Address Byte and the Word  
Address Bytes. This gives the master access to any  
one of the words in the array or CCR. (Note: Prior to  
writing to the CCR, the master must write a 02h, then  
06h to the status register in preceding operations to  
enable the write operation. See “Writing to the Clock/  
Control Registers” on page 6.) Upon receipt of each  
address byte, the X1243 responds with an acknowl-  
edge. After receiving both address bytes the X1243  
awaits the eight bits of data. After receiving the 8 data  
bits, the X1243 again responds with an acknowledge.  
The master then terminates the transfer by generating  
a stop condition. The X1243 then begins an internal  
write cycle of the data to the nonvolatile memory. Dur-  
ing the internal write cycle, the device inputs are dis-  
abled, so the device will not respond to any requests  
from the master. The SDA output is at high impedance.  
See Figure 6.  
The device will respond with an acknowledge after rec-  
ognition of a start condition and if the correct Device  
Identifier and Select bits are contained in the Slave  
Address Byte. If a write operation is selected, the  
device will respond with an acknowledge after the  
receipt of each subsequent eight bit word. The device  
will acknowledge all incoming data and address bytes,  
except for:  
– The Slave Address Byte when the Device Identifier  
and/or Select bits are incorrect  
– All Data Bytes of a write when the WEL in the Write  
Protect Register is LOW  
– The 2nd Data Byte of a Register Write Operation  
(when only 1 data byte is allowed)  
A write to a protected block of memory is ignored, but  
will still receive an acknowledge. At the end of the write  
command, the X1243 will not initiate an internal write  
cycle, and will continue to ACK commands.  
In the read mode, the device will transmit eight bits of  
data, release the SDA line, then monitor the line for an  
acknowledge. If an acknowledge is detected and no  
stop condition is generated by the master, the device  
will continue to transmit data. The device will terminate  
further data transmissions if an acknowledge is not  
detected. The master must then issue a stop condition  
to return the device to Standby mode and place the  
device into a known state.  
Characteristics subject to change without notice. 8 of 18  
REV 1.1.4 5/31/01  
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