X1243 – Preliminary Information
initiate another change to the CCR contents. If the
sequence is not completed for any reason (by send-
ing an incorrect number of bits or sending a start
instead of a stop, for example) the RWEL bit is not
reset and the device remains in an active mode.
SERIAL COMMUNICATION
Interface Conventions
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data
transfers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this family
operate as slaves in all applications.
– Writing all zeros to the status register resets both the
WEL and RWEL bits.
– A read operation occurring between any of the previ-
ous operations will not interrupt the register write
operation.
– The RWEL and WEL bits can be reset by writing a 0
to the Status Register.
Figure 3. Valid Data Changes on the SDA Bus
SCL
SDA
Data Stable
Data Change
Data Stable
Clock and Data
SCL lines for the start condition and will not respond to
any command until this condition has been met. See
Figure 4.
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 3.
Stop Condition
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the Standby power mode after a read
sequence. A stop condition can only be issued after
the transmitting device has released the bus Refer to
Figure 4.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The device continuously monitors the SDA and
Figure 4. Valid Start and Stop Conditions
SCL
SDA
Start
Stop
Characteristics subject to change without notice. 7 of 18
REV 1.1.4 5/31/01
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