X1243 – Preliminary Information
DEVICE ADDRESSING
Following the Slave Byte is a two byte word address.
The word address is either supplied by the master
device or obtained from an internal counter. On power
up the internal address counter is set to address 0h, so
a current address read of the EEPROM array starts at
address 0. When required, as part of a random read,
the master device must supply the 2 Word Address
Bytes.
Following a start condition, the master must output a
Slave Address Byte. The first four bits of the Slave
Address Byte specify access to the EEPROM array or
to the CCR. Slave bits ‘1010’ access the EEPROM
array. Slave bits ‘1101’ access the CCR.
Bit 3 through Bit 1 of the slave byte specify the device
select bits.These are set to ‘111’.
In a random read operation, the slave byte in the
“dummy write” portion must match the slave byte in the
“read” section. That is if the random read is from the
array the slave byte must be ‘1010111x’ in both
instances. Similarly, for a random read of the Clock/
Control Registers, the slave byte must be ‘1101111x’ in
both places.
The last bit of the Slave Address Byte defines the oper-
ation to be performed. When this R/W bit is a one, then
a read operation is selected. A zero selects a write
operation. Refer to Figure 12.
After loading the entire Slave Address Byte from the
SDA bus, the device compares the device identifier
and device select bits with ‘1010111’ or ‘1101111’.
Upon a correct compare, the device outputs an
acknowledge on the SDA line.
Figure 12. Sequential Read Sequence
Signals from
Slave
S
t
o
p
the Master
A
C
K
A
C
K
A
C
K
Address
SDA Bus
1
A
C
K
Signals from
the Slave
Data
(2)
Data
(n-1)
Data
(1)
Data
(n)
(n is any integer greater than 1)
Figure 13. Slave Address, Word Address, and Data Bytes (64-Byte Pages)
Device Identifier
Slave Address Byte
Array
CCR
1
1
0
1
1
0
0
1
R/W
A8
1
1
1
Byte 0
High Order Word Address
0
0
0
0
0
A10
A9
Byte 1
Low Order Word Address
A7
D7
A6
D6
A5
D5
A4
D4
A3
D3
A2
D2
A1
D1
A0
D0
Byte 2
Data Byte
Byte 3
Characteristics subject to change without notice. 12 of 18
REV 1.1.4 5/31/01
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