X1243 – Preliminary Information
Figure 6. Byte Write Sequence
S
t
a
r
Signals from
the Master
S
t
o
p
Word
Address 1
Word
Address 0
Slave
Address
Data
t
SDA Bus
1
1 1 1 0
0 0 0 0 0
A
C
K
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Figure 7. Writing 30 bytes to a 64-byte page starting at address 40.
7 Bytes
23 Bytes
Address Pointer
Ends Here
Addr = 7
Address
40
Address
= 6
Address
63
Figure 8. Page Write Sequence
S
(1 ≤ n ≤ 64)
t
a
r
Signals from
the Master
S
t
o
p
Word
Address 1
Slave
Address
Word
Address 0
Data
(1)
Data
(n)
t
SDA Bus
1
1 1 1 0
0 0 0 0 0
A
C
K
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Page Write
the page, it “rolls over” and goes back to the first
address on the same page. This means that the mas-
ter can write 64-bytes to a memory array page or
8-bytes to a CCR section starting at any location on
that page. If the master begins writing at location 40 of
the memory and loads 30 bytes, then the first 23-bytes
are written to addresses 40 through 63, and the last
7-bytes are written to columns 0 through 6. Afterwards,
the address counter would point to location 7 on the
page that was just written. If the master supplies more
than the maximum bytes in a page, then the previously
loaded data is over written by the new data, one byte at
a time.
The X1243 has a page write operation. It is initiated in
the same manner as the byte write operation; but instead
of terminating the write cycle after the first data byte is
transferred, the master can transmit up to 63 more bytes
to the memory array and up to 7 more bytes to the
clock/control registers.
(Note: Prior to writing to the CCR, the master must
write a 02h, then 06h to the status register in two pre-
ceding operations to enable the write operation. See
“Writing to the Clock/Control Registers” on page 6.)
After the receipt of each byte, the X1243 responds with
an acknowledge, and the address is internally incre-
mented by one. When the counter reaches the end of
Characteristics subject to change without notice. 9 of 18
REV 1.1.4 5/31/01
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