X1243 – Preliminary Information
CONTROL REGISTERS
A match of the RTC and the contents of the alarm 1
registers automatically sets the AL1 bit. If the AL1E bit
is also set, the output IRQ signal goes active (LOW). If
the AL1E bit is not set, the AL1 bit is set, but the IRQ
signal remains unchanged.
Block Protect Bits—BP2, BP1, BP0 (Nonvolatile)
The Block Protect Bits, BP2, BP1 and BP0, determine
which blocks of the array are write protected. A write to
a protected block of memory is ignored. The block pro-
tect bits will prevent write operations to one of eight
segments of the array. The partitions are described in
Table 3.
Reading the status register, containing the AL0 and
AL1 bits, resets the bits. The bits do not reset until the
falling edge of the 8th output clock of the status register
containing the Alarm bits. When the bits reset, the out-
put IRQ signal returns to the inactive state.
Table 3. Block Protect Bits
Protected Addresses
Pulsed Interrupt Mode (IM Bit = 1)
X1243
Array Lock
None
In this mode, the alarm interrupt enable bits (AL0E and
AL1E) are not used. Alarm 1 operates as before, so a
match of the RTC and Alarm 1 sets the AL1 bit. Since
the interrupt enable bits have no function, it is neces-
sary for the host processor to poll the AL1 bit to deter-
mine if an alarm has occurred.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
None
600 - 7FF
h
Upper 1/4
Upper 1/2
Full Array
First Page
First 2 pgs
First 4 pgs
First 8 pgs
h
h
h
400 - 7FF
h
000 - 7FF
h
000 - 03F
h
h
h
Alarm 0 provides an output response. In this case,
when the RTC matches the Alarm 0 registers, the out-
put IRQ pulses one time. This pulse can be used to
control some outside circuit or event, without the need
for a local processor. The duration of the pulse is 1024
cycles of the 32.748kHz oscillator. All alarm 0 enable
options are available, so this becomes a very flexible
long term repeat trigger.
000 - 07F
h
000 - 0FF
h
h
h
000 - 1FF
h
Interrupt Control Bits (AL1E, AL0E)
There are two Interrupt Control bits, Alarm 1 Interrupt
Enable (AL1E) and Alarm 0 Interrupt Enable (AL0E) to
specifically enable or disable the alarm interrupt signal
output. The interrupt output is enabled when either bit is
set to ‘1’. Two volatile bits (AL1 and AL0), associated
with these alarms, indicate if an alarm has happened.
These bits are set on an alarm condition regardless of
whether the alarm interrupts are enabled. The AL1 and
AL0 bits are reset by the falling edge of the 8th clock of
a read of the register containing the bits.
WRITING TO THE CLOCK/CONTROL REGISTERS
Changing any of the nonvolatile bits of the clock/control
register requires the following steps:
– Write a 02H to the Status Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation pre-
ceeded by a start and ended with a stop).
– Write a 06H to the Status Register to set both the
Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation preceeded by a start
and ended with a stop).
In an alternative mode (called pulsed interrupt mode),
controlled by an interrupt mode (IM) bit, the alarm 0
setting provides an output pulse on IRQ each time the
alarm matches the RTC. In this case the AL0 bit is not
used. Alarm 1 works as before (i.e. the AL1 bit is set
when an alarm occurs), but it is necessary to poll the sta-
tus register to determine whether a match has occurred.
This read operation is necessary to reset the AL1 flag.
– Write one to 8 bytes to the Clock/Control Registers
with the desired clock, alarm, or control data. This
sequence starts with a start bit, requires a slave byte
of “11011110” and an address within the CCR and is
terminated by a stop bit. A write to the CCR changes
EEPROM values so these initiate a nonvolatile write
cycle and will take up to 10ms to complete. Writes to
undefined areas have no effect. The RWEL bit is
reset by the completion of a nonvolatile write write
cycle, so the sequence must be repeated to again
Normal Mode (IM Bit = 0)
A match of the RTC and the contents of the alarm 0
registers automatically sets the AL0 bit. If the AL0E bit
is also set, the output IRQ signal goes active (LOW). If
the AL0E bit is not set, the AL0 bit is set, but the IRQ
signal remains unchanged.
Characteristics subject to change without notice. 6 of 18
REV 1.1.4 5/31/01
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