X1243 – Preliminary Information
The master terminates the Data Byte loading by issu-
ing a stop condition, which causes the device to begin
the nonvolatile write cycle. As with the byte write oper-
ation, all inputs are disabled until completion of the
internal write cycle. Refer to Figure 8 for the address,
acknowledge, and data transfer sequence.
Figure 9. Acknowledge Polling Sequence
Byte Load Completed
by Issuing STOP.
Enter ACK Polling
Issue START
Issue Slave
Address Byte
(Read or Write)
Stops and Write Modes
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte and it’s associated ACK signal. If a stop is issued
in the middle of a data byte, or before 1 full data byte +
ACK is sent, then the device will reset itself without
performing the write. The contents of the array will not
be affected.
Issue STOP
NO
NO
ACK
Returned?
YES
Acknowledge Polling
The disabling of the inputs during nonvolatile write
cycles can be used to take advantage of the typical
5ms write cycle time. Once the stop condition is issued
to indicate the end of the master’s byte load operation,
the device initiates the internal nonvolatile write cycle.
Acknowledge polling can be initiated immediately. To
do this, the master issues a start condition followed by
the Slave Address Byte for a write or read operation. If
the device is still busy with the nonvolatile write cycle
then no ACK will be returned. If the device has com-
pleted the write operation, an ACK will be returned and
the host can then proceed with the read or write opera-
tion. Refer to the flow chart in Table 9.
Nonvolatile Write
Cycle Complete.
Continue Command
Sequence?
Issue STOP
YES
Continue Normal
Read or Write
Command
Sequence
PROCEED
READ OPERATIONS
Upon receipt of the Slave Address Byte with the R/W
bit set to one, the device issues an acknowledge and
then transmits the eight bits of the Data Byte. The mas-
ter terminates the read operation when it does not
respond with an acknowledge during the ninth clock
and then issues a stop condition. Refer to Figure 10 for
the address, acknowledge, and data transfer sequence.
There are three basic read operations: Current
Address Read, Random Read, and Sequential Read.
Current Address Read
Internally the device contains an address counter that
maintains the address of the last word read incre-
mented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n + 1. On power up, the sixteen bit
address is initialized to 0h. In this way, a current
address read can be initiated immediately after the
power on reset to download the contents of memory
starting at the first location.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
Characteristics subject to change without notice. 10 of 18
REV 1.1.4 5/31/01
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