X1241 – Preliminary Information
Figure 13. Acknowledge Polling Sequence
Upon receipt of the Slave Address Byte with the R/W
bit set to one, the device issues an acknowledge and
then transmits the eight bits of the Data Byte. The mas-
ter terminates the read operation when it does not
respond with an acknowledge during the ninth clock
and then issues a stop condition. Refer to Figure 10 for
the address, acknowledge, and data transfer
sequence.
Byte Load Completed
by Issuing STOP.
Enter ACK Polling
Issue START
Issue Slave
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
Issue STOP
Address Byte
(Read or Write)
NO
NO
ACK
Returned?
YES
Nonvolatile Write
Cycle Complete.
Continue Command
Sequence?
Issue STOP
YES
Continue Normal
Read or Write
Command
Sequence
PROCEED
Figure 14. Current Address Read Sequence
S
t
S
t
o
p
Slave
Address
Signals from
the Master
a
r
t
SDA Bus
1
1 1 1 1
A
C
K
Signals from
the Slave
Data
Characteristics subject to change without notice. 12 of 22
REV 1.1.3 2/13/01
www.xicor.com
XICOR [ XICOR INC. ]
