WM8983
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OUTPUT CONFIGURATION
L/ROUT2EN/
OUT3/4EN
OUT3BOOST/
VROI
OUT4BOOST/
SPKBOOST
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
X
X
1kΩ tie-off to AVDD1/2
30kΩ tie-off to AVDD1/2
1kΩ tie-off to 1.5xAVDD1/2
30kΩ tie-off to 1.5xAVDD1/2
Output enabled (DC level=AVDD1/2)
Output enabled (DC level=1.5xAVDD1/2)
Table 45 Unused Output Pin Bias Options
DIGITAL AUDIO INTERFACES
The audio interface has four pins:
•
•
•
•
ADCDAT: ADC data output
DACDAT: DAC data input
LRC: Data Left/Right alignment clock
BCLK: Bit clock, for synchronisation
The clock signals BCLK, and LRC can be outputs when the WM8983 operates as a master, or inputs
when it is a slave (see Master and Slave Mode Operation, below).
Five different audio data formats are supported:
•
•
•
•
•
Left justified
Right justified
I2S
DSP mode early
DSP mode late
All of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the
Electrical Characteristic section for timing information.
MASTER AND SLAVE MODE OPERATION
The WM8983 audio interface may be configured as either master or slave. As a master interface
device the WM8983 generates BCLK and LRC and thus controls sequencing of the data transfer on
ADCDAT and DACDAT. To set the device to master mode register bit MS should be set high. In
slave mode (MS=0), the WM8983 responds with data to clocks it receives over the digital audio
interfaces.
AUDIO DATA FORMATS
In Left Justified mode, the MSB is available on the first rising edge of BCLK following an LRC
transition. The other bits up to the LSB are then transmitted in order. Depending on word length,
BCLK frequency and sample rate, there may be unused BCLK cycles before each LRC transition.
Figure 35 Left Justified Audio Interface (assuming n-bit word length)
PP Rev 1.1 August 2005
62
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
