WM8961
Pre-Production
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
Timeout/slow clock divider setting
00 : 125Hz
01 : 250Hz
10 : 500Hz
11 : 1kHz
R30 (1Eh)
Clocking 3
8:7
CLK_TO_DIV[1:0]
00
256kHz clock divider setting
000000 : SYSCLK/1
000001 : SYSCLK/2
…
6:1
CLK_256K_DIV[5:0]
10_1111
101111 : SYSCLK/48 (default)
…
111110 : SYSCLK/63
111111 : SYSCLK/64
Manual clock configuration Enable
0
MANUAL_MODE
1
0 = When low, use SAMPLE_RATE & CLK_SYS_RATE to allow
automatic configuration of system clock dividers. Excludes master
mode audio interface clocks.
1 = manual configuration of system clock dividers.
Register 1Eh Clocking 3
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
Left microphone boost control
00 : 0dB
01 : 13dB
R32 (20h)
ADCL signal
path
5:4
LMICBOOST[1:0]
00
10 : 20dB
11 : 29dB
Register 20h ADCL signal path
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
Right microphone boost control
00 : 0dB
01 : 13dB
R33 (21h)
ADCR signal
path
5:4
RMICBOOST[1:0]
00
10 : 20dB
11 : 29dB
Register 21h ADCR signal path
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R40 (28h)
LOUT2
8
7
SPKVU
SPKLZC
0
0
Speaker PGA volume update
Left Speaker PGA zero cross enable
volume
Left Speaker output PGA gain, 1dB steps
6:0
SPKLVOL[6:0]
000_0000
0000000 to 0101111 : Mute
0110000 : -73dB
…
1111001 : 0dB
…
1111111 : +6dB
Register 28h LOUT2 volume
PP, August 2009, Rev 3.1
w
93
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
