Production Data
WM8945
Power Up (Video signal DC coupled to Video Buffer input):
ACTION
LABEL
REGISTER[BITS]
Turn on external supplies and wait for the
supply voltages to settle.
Reset registers to default state (software
reset)
SW_RESET
R0 (00h) [15:0]
VMID_FAST_START = 1
STARTUP_BIAS_ENA = 1
BIAS_SRC = 1
R7 (07h) [11]
R7 (07h) [8]
R7 (07h) [7]
R7 (07h) [6:5]
Enable VMID Fast Start and Start up
Bias
Select Start-Up Bias and set VMID soft
start for start-up ramp
VMID_RAMP[1:0] = 01
If using VMID as the reference voltage
for the LDO then select VMID fast start or
set to 0 if using the Bandgap as the
reference voltage for LDO.
LDO_REF_SEL_FAST = 1
LDO_BIAS_SRC = 1
R53 (35h) [14]
R53 (35h) [5]
Select LDO Start-Up Bias and enable
LDO
LDO_ENA = 1
R53 (35h) [15]
Delay 300ms for LDO to settle
BIAS_ENA = 1
VMID_BUF_ENA = 1
R2 (02h) [3]
R2 (02h) [2]
Enable VMID Buffer and Master Bias
Set VMID_SEL[1:0] for fast start-up
VMID_SEL[1:0] = 11
R2 (02h) [1:0]
Enable VMID
VMID_ENA = 1
R7 (07h) [4]
Delay 150ms to allow VMID to settle
LDO_REF_SEL_FAST = 0
LDO_BIAS_SRC = 0
R53 (35h) [14]
R53 (35h) [5]
Set LDO for normal operation
Set VMID for normal operation
VMID_FAST_START = 0
STARTUP_BIAS_ENA = 0
R7 (07h) [11]
R7 (07h) [8]
Set VMID divider for normal operation
Set Video Buffer Gain as required
VMID_SEL = 01
VB_GAIN
R2 (02h) [1:0]
R38 (26h) [5]
Set Video Buffer Filter Q Boost as
required
VB_QBOOST
VB_ENA = 1
R38 (26h) [6]
R38 (26h) [7]
Enable video buffer
AUXILIARY ADC
The WM8945 incorporates a low-power 12-bit Auxiliary ADC (AUXADC). This can be used to
measure the SPKVDD supply voltage and to measure other analogue voltages connected to the
AUX1 or AUX2 inputs. The Auxiliary ADC is powered from LDOVDD – typically 3.3V.
The AUXADC is also used to perform Touch Panel measurements; these are interleaved with the
AUXADC measurement requests; see “Touch Panel Controller” for further details.
The AUXADC is powered on the TPVDD (internal) power domain; internal resistor dividers enable
SPKVDD voltages greater TPVDD to be measured by the AUXADC.
AUXADC CONTROL
The AUXADC is enabled by setting the AUX_ENA register bit.
The AUXADC measurements can be initiated manually or automatically. For automatic operation, the
AUX_RATE register is set according to the required conversion rate, and conversions are enabled by
setting the AUX_CVT_ENA bit. For manual operation, the AUX_RATE register is set to 00h, and each
manual conversion is initiated by setting the AUX_CVT_ENA bit. In manual mode, the
AUX_CVT_ENA bit is reset by the WM8945 after each conversion request.
PD, May 2011, Rev 4.1
83
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
