WM8945
Production Data
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R4 (04h)
DACDATA_
PULL [1:0]
DACDAT pull-up / pull-down Enable
00 = no pull-up or pull-down
01 = pull-down
15:14
00
Audio
interface
10 = pull-up
11 = reserved
FRAME_PULL
[1:0]
LRCLK pull-up / pull-down Enable
00 = no pull-up or pull-down
01 = pull-down
13:12
11:10
00
00
10 = pull-up
11 = reserved
BCLK_PULL
[1:0]
BCLK pull-up / pull-down Enable
00 = no pull-up or pull-down
01 = pull-down
10 = pull-up
11 = reserved
Table 48 Pull-Up and Pull-Down Control
CLOCKING AND SAMPLE RATES
The internal clocks for the CODEC and Digital Audio Interface are derived from a common internal
clock source, SYSCLK. This clock can either be derived directly from MCLK, or may be generated
using the Frequency Locked Loop (FLL) using MCLK as a reference. All commonly-used audio
sample rates can be derived directly from typical MCLK frequencies; the FLL provides additional
flexibility for a wider range of MCLK frequencies.
The WM8945 supports a wide range of standard audio sample rates from 8kHz to 48kHz. When the
ADC and DAC are both enabled, they operate at the same sample rate, fs.
Other functions such as the AUXADC, Touch Panel controller, Interrupts, GPIO input de-bounce and
PGA zero-cross timeouts are clocked using a free-running oscillator.
The control registers associated with Clocking and Sample Rates are described in Table 49.
The overall clocking scheme for the WM8945 is illustrated in Figure 31.
Figure 31 WM8945 Clocking Overview
PD, May 2011, Rev 4.1
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
