Pre-Production
WM8904
DIGITAL AUDIO INTERFACE CONTROL
The register bits controlling audio data format, word length, left/right channel data source and TDM
are summarised in Table 54.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R24 (18h)
Left Digital Audio channel source
7
AIFADCL_SR
C
0
Audio
Interface 0
0 = Left ADC data is output on left channel
1 = Right ADC data is output on left channel
Right Digital Audio channel source
6
AIFADCR_SR
C
1
0 = Left ADC data is output on right channel
1 = Right ADC data is output on right
channel
Left DAC Data Source Select
0 = Left DAC outputs left channel data
1 = Left DAC outputs right channel data
Right DAC Data Source Select
0 = Right DAC outputs left channel data
1 = Right DAC outputs right channel data
DAC TDM Enable
5
4
AIFDACL_SR
C
0
1
0
0
0
0
0
0
AIFDACR_SR
C
R25 (19h)
13
12
11
10
7
AIFDAC_TDM
Audio
Interface 1
0 = Normal DACDAT operation
1 = TDM enabled on DACDAT
DACDAT TDM Channel Select
0 = DACDAT data input on slot 0
1 = DACDAT data input on slot 1
ADC TDM Enable
AIFDAC_TDM
_CHAN
AIFADC_TDM
0 = Normal ADCDAT operation
1 = TDM enabled on ADCDAT
ADCDAT TDM Channel Select
0 = ADCDAT outputs data on slot 0
1 = ADCDAT output data on slot 1
BCLK Invert
AIFADC_TDM
_CHAN
AIF_BCLK_IN
V
0 = BCLK not inverted
1 = BCLK inverted
LRC Polarity / DSP Mode A-B select.
Right, left and I2S modes – LRC polarity
0 = Not Inverted
4
AIF_LRCLK_I
NV
1 = Inverted
DSP Mode – Mode A-B select
0 = MSB is available on 2nd BCLK rising
edge after LRC rising edge (mode A)
1 = MSB is available on 1st BCLK rising
edge after LRC rising edge (mode B)
Digital Audio Interface Word Length
00 = 16 bits
3:2
1:0
AIF_WL [1:0]
AIF_FMT [1:0]
10
10
01 = 20 bits
10 = 24 bits
11 = 32 bits
Digital Audio Interface Format
00 = Right Justified
01 = Left Justified
10 = I2S
11 = DSP
Table 54 Digital Audio Interface Data Control
PP, Rev 3.3, September 2012
97
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
