Pre-Production
WM8904
GPIO OUTPUTS FROM FLL
The WM8904 has an internal signal which indicates whether the FLL Lock has been achieved. The
FLL Lock status is an input to the Interrupt control circuit and can be used to trigger an Interrupt event
- see “Interrupts”.
The FLL Lock signal can be output directly on a GPIO pin as an external indication of FLL Lock. See
“General Purpose Input/Output (GPIO)” for details of how to configure a GPIO pin to output the FLL
Lock signal.
The FLL Clock can be output directly on a GPIO pin as a clock signal for other circuits. Note that the
FLL Clock may be output even if the FLL is not selected as the WM8904 SYSCLK source. The
clocking configuration is illustrated in Figure 59. See “General Purpose Input/Output (GPIO)” for
details of how to configure a GPIO pin to output the FLL Clock.
EXAMPLE FLL CALCULATION
To generate 12.288 MHz output (FOUT) from a 12.000 MHz reference clock (FREF):
Set FLL_CLK_REF_DIV in order to generate FREF <=13.5MHz:
FLL_CLK_REF_DIV = 00 (divide by 1)
Set FLL_CTRL_RATE to the recommended setting:
FLL_CTRL_RATE = 000 (divide by 1)
Set FLL_GAIN to the recommended setting:
FLL_GAIN = 0000 (multiply by 1)
Set FLL_OUTDIV for the required output frequency as shown in Table 69:-
FOUT = 12.288 MHz, therefore FLL_OUTDIV = 07h (divide by 8)
Set FLL_FRATIO for the given reference frequency as shown in Table 70:
REF = 12MHz, therefore FLL_FRATIO = 0h (divide by 1)
F
Calculate FVCO as given by FVCO = FOUT x FLL_OUTDIV:-
VCO = 12.288 x 8 = 98.304MHz
F
Calculate N.K as given by N.K = FVCO / (FLL_FRATIO x FREF):
N.K = 98.304 / (1 x 12) = 8.192
Determine FLL_N and FLL_K from the integer and fractional portions of N.K:-
FLL_N is 8. FLL_K is 0.192
Confirm that N.K is a fractional quantity and set FLL_FRACN_ENA:
N.K is fractional. Set FLL_FRACN_ENA = 1.
Note that, if N.K is an integer, then an alternative value of FLL_FRATIO should be selected
in order to produce a fractional value of N.K.
PP, Rev 3.3, September 2012
113
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
