WM8805
Production Data
PIN DESCRIPTION
PIN
NAME
DVDD
RX1
Type
Supply
DESCRIPTION
1
Digital core supply
2
Digital In
Digital In
Digital In/Out
S/PDIF receive channel 1
S/PDIF receive channel 0
3
RX0
4
SCLK
Control interface clock / TRANS_ERR flag in hardware control mode. See
note 2.
5
GPO0 / SWIFMODE
Digital In/Out
General purpose digital output or selected functionality at hardware reset.
See note 2.
6
7
GPO1
Digital Out
General purpose digital output
SDIN / HWMODE
Digital Input
Control interface data input and hardware/software mode select at hardware
reset. See note 2.
8
9
SDOUT / GPO7
CSB / GPO2
Digital In/Out
Digital In/Out
Control interface data output / NON_AUDIO flag in hardware control mode /
GPO in 2-wire software control mode. See note 2.
Chip select / UNLOCK flag in hardware control mode / GPO in 2-wire
software control mode. See note 2.
System reset (active low)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
RESETB
PVDD
Digital Input
Supply
PLL core supply
PGND
Supply
PLL ground
CLKOUT
XOP
Digital Out
Digital Output
Digital Input
Digital Out
Digital In
High drive clock output at 64fs, 128fs, 256fs and 512fs
Crystal output
XIN
Crystal input
DOUT
Audio interface data output
DIN
Audio interface data input
BCLK
Digital In/Out
Digital In/Out
Digital In/Out
Digital Out
Digital In/Out
Digital In/Out
Digital In/Out
Digital In/Out
Digital In
Audio interface bit clock
LRCLK
MCLK
Audio interface left/right word clock
Master clock input or output
TX0
S/PDIF transmit
RX7 / GPO6
RX6 / GPO5
RX5 / GPO4
RX4 / GPO3
RX3
S/PDIF receive channel 7 or general purpose digital output
S/PDIF receive channel 6 or general purpose digital output
S/PDIF receive channel 5 or general purpose digital output
S/PDIF receive channel 4 or general purpose digital output
S/PDIF receive channel 3
RX2
Digital In
S/PDIF receive channel 2
DGND
Supply
Digital ground
Notes:
1. Digital input pins have Schmitt trigger input buffers.
2. Refer to Table 6 Device Configuration at Power up or Hardware Reset
PD Rev 4.1 September 07
4
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