WM8777
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0001110
(0Eh)
7:0
RDA2[7:0]
11111111
(0dB)
Digital Attenuation control for DAC2 Right Channel (LFESOP) in
0.5dB steps. See Table 63
Digital
Attenuation
DACR2
8
UPDATE
Not latched
Controls simultaneous update of all Attenuation Latches
0 = Store RDA2 in intermediate latch (no change to output)
1 = Store RDA2 and update attenuation on all channels.
0001111
(0Fh)
7:0
8
LDA3[7:0]
UPDATE
11111111
(0dB)
Digital Attenuation control for DAC3 Left Channel (LSURSOP) in
0.5dB steps. See Table 63
Digital
Attenuation
DACL3
Not latched
Controls simultaneous update of all Attenuation Latches
0 = Store LDA3 in intermediate latch (no change to output)
1 = Store LDA3 and update attenuation on all channels.
0010000
(10h)
7:0
8
RDA3[7:0]
UPDATE
11111111
(0dB)
Digital Attenuation control for DAC3 Right Channel (RSURSOP) in
0.5dB steps. See Table 63
Digital
Attenuation
DACR3
Not latched
Controls simultaneous update of all Attenuation Latches
0 = Store RDA3 in intermediate latch (no change to output)
1 = Store RDA3 and update attenuation on all channels.
0010001
(11h)
7:0
8
LDA4[7:0]
UPDATE
11111111
(0dB)
Digital Attenuation control for DAC4 Left Channel (LAUXSOP) in
0.5dB steps. See Table 63
Digital
Attenuation
DACL4
Not latched
Controls simultaneous update of all Attenuation Latches
0 = Store LDA4 in intermediate latch (no change to output)
1 = Store LDA4 and update attenuation on all channels.
0010010
(12h)
7:0
8
RDA4[7:0]
UPDATE
11111111
(0dB)
Digital Attenuation control for DAC4 Right Channel (RAUXSOP) in
0.5dB steps. See Table 63
Digital
Attenuation
DACR4
Not latched
Controls simultaneous update of all Attenuation Latches
0 = Store RDA4 in intermediate latch (no change to output)
1 = Store RDA4 and update attenuation on all channels.
0010011
(13h)
7:0
8
MASTDA[7:0]
UPDATE
11111111
(0dB)
Digital Attenuation control for all DAC channels in 0.5dB steps.
See Table 63
Digital
Attenuation
Not latched
Controls simultaneous update of all Attenuation Latches
0 = Store gain in intermediate latch (no change to output)
1 = Store gain and update attenuation on all channels.
Master
(all channels)
0010100
(14h)
7:0
PHASE[7:0]
00000000
Controls phase of DAC outputs
PHASE[0] = 1 inverts phase of DAC1L output
PHASE[1] = 1 inverts phase of DAC1R output
PHASE[2] = 1 inverts phase of DAC2L output
PHASE[3] = 1 inverts phase of DAC2R output
PHASE[4] = 1 inverts phase of DAC3L output
PHASE[5] = 1 inverts phase of DAC3R output
PHASE[6] = 1 inverts phase of DAC4L output
PHASE[7] = 1 inverts phase of DAC4R output
DAC Digital Volume Zero Cross Enable:
0 = Zero Cross detect disabled
DAC Output
Phase
0010101
(15h)
0
1
DZCEN
0
0
DAC Attenuation
Control
1 = Zero Cross detect enabled
DACATC
Attenuator Control
0 = All DACs use attenuations as programmed.
1 = Right channel DACs use corresponding left DAC
attenuations
2
4
IZD
0
0
Infinite zero detection circuit control and automute control
0 = Infinite zero detect automute disabled
1 = Infinite zero detect automute enabled
DAC Analogue Zero cross detect timeout disable
0 = Timeout enabled
TOCDAC
1 = Timeout disabled
PP Rev 1.94 November 2004
78
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
