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WM8777
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
6
SPDIFTXD
1
SPDIF_TX powerdown
0 = SPDIF_TX enabled
1 = SPDIF_TX disabled
SPDIF_RX powerdown
7
8
SPDIFRXD
OSCPD
1
1
0 = SPDIF_RX enabled
1 = SPDIF_RX disabled
OSC power down
0 = Oscillator enabled
1 = Oscillator disabled
0011011
(1Bh)
1:0
PAIFTX_FMT
[1:0]
10
Interface format select
00 = right justified mode
01 = left justified mode
10 = I2S mode
Primary
Interface
Control (TX)
11 = DSP (early or late) mode
2
PAIFTX_LRP
0
PDATAOPLRC Polarity or DSP Early/Late mode select
Left Justified / Right Justified /
I2S
DSP Mode
0 = Early DSP mode
1 = Late DSP mode
0 =Standard PDATAOPLRC
Polarity
1 =Inverted PDATAOPLRC
Polarity
3
PAIFTX_BCP
0
ADCPBCLK/PBCLK Polarity
0 = Normal ADCPBCLK/PBCLK.
1 = Inverted ADCPBCLK/PBCLK.
5:4
PAIFTX_WL
[1:0]
10
Input Word Length
00 = 16-bit Mode
01 = 20-bit Mode
10 = 24-bit Mode
11 = 32-bit Mode (not supported in right justified mode)
ADC Highpass Filter Disable:
0 = Highpass Filter enabled
1 = Highpass Filter disabled
ADC oversample rate select
0 = 128x oversampling
1 = 64x oversapmling
Sync ADC and DAC together.
0 = Enable SYNC function
1 = Disable Sync function
Limiter threshold/ALC target level in 1dB steps.
0000: -16dB FS
6
7
ADCHPD
ADCOSR
SYNC
0
0
0
8
0011101
(1Dh)
3:0
LCT[3:0]
1011
(-6dB)
ALC Control 1
0001: -15dB FS
…
1101: -3dB FS
1110: -2dB FS
1111: -1dB FS
6:4
MAXGAIN[2:0]
111
(+24dB)
Set Maximum Gain of PGA
111 = +24dB
110 = +20dB
….(-4dB steps)
010 = +4dB
001 = 0dB
000 = 0dB
8:7
LCSEL[1:0]
00
ALC/Limiter function select
00 = Limiter
(OFF)
01 = ALC Right channel only
10 = ALC Left channel only
11 = ALC Stereo (PGA registers unused)
PP Rev 1.94 November 2004
81
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
