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WM8777
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
8:5
PL[3:0]
1001
DAC Output Control
PL[3:0]
Left
Right
PL[3:0]
Left
Right
Output
Output
Mute
Mute
Mute
Mute
Left
Output
Output
0000
0001
0010
0011
0100
0101
0110
0111
Mute
Left
1000
1001
1010
1011
1100
1101
1110
1111
Mute
Right
Left
Right
Right
(L+R)/2
Mute
Left
Right
(L+R)/2
Mute
Right
Right
(L+R)/2
(L+R)/2
(L+R)/2
(L+R)/2
Left
Left
Right
(L+R)/2
Left
Right
(L+R)/2
Left
0010110
(16h)
3:0
DMUTE[3:0]
0000
DAC channel soft mute enables:
DMUTE[0] = 1, enable softmute on DAC1.
DMUTE[1] = 1, enable softmute on DAC2.
DMUTE[2] = 1, enable softmute on DAC3.
DMUTE[3] = 1, enable softmute on DAC4.
DAC channel master soft mute. Mutes all DAC channels:
0 = disable softmute on all DACs.
1 = enable softmute on all DACs.
RECL Output Enable
Mute Control
4
MUTEALL
RECLEN
0
6:5
00
00 = REC output muted
01 = REC output ADCL
10 = REC output DAC1L
8:7
3:0
RECREN
00
RECR Output Enable
00 = REC output muted
01 = REC output ADCR
10 = REC output DAC1R
0010111
(17h)
DEEMP[3:0]
0000
De-emphasis mode select:
DEEMPH[0] = 1, enable De-emphasis on DAC1.
DEEMPH[1] = 1, enable De-emphasis on DAC2.
DEEMPH[2] = 1, enable De-emphasis on DAC3.
DEEMPH[3] = 1, enable De-emphasis on DAC4.
DAC Control
7:4
1:0
DZFM[3:0]
0000
10
Selects the ouput for ZFLG1 and ZFLG2 pins (see Table 53).
1 = indicates 1024 consecutive zero input samples on the
channels selected
0 = indicates at least one of selected channels has non
zero sample in last 1024 inputs
0011000
(18h)
PAIFRX_FMT
[1:0]
Interface format select
00 = right justified mode
Primary
01 = left justified mode
10 = I2S mode
Interface
Control (RX)
11 = DSP (early or late) mode
PDATAIPLRC Polarity or DSP Early/Late mode select
2
PAIFRX_LRP
PAIFRX_BCP
0
Left Justified / Right Justified /
I2S
DSP Mode
0 = Early DSP mode
1 = Late DSP mode
0 =Standard PDATAIPLRC
Polarity
1 =Inverted PDATAIPLRC
Polarity
3
0
PBCLK Polarity
0 = Normal - DIN[3:0], PDATAIPLRC and PDATAOPLRC
sampled on rising edge of PBCLK; PDATAOP changes on
falling edge of PBCLK.
1 = Inverted - DIN[3:0], PDATAIPLRC and PDATAOPLRC
sampled on falling edge of PBCLK; PDATAOP changes on
rising edge of PBCLK.
PP Rev 1.94 November 2004
79
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
