Product Preview
WM8777
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0000110
(06h)
6:0
AUXLA[6:0]
1101011
(0dB)
0
Analogue Attenuation control for AUXL in 1dB steps. See Table
60.
Analogue
Attenuation
AUXL
7
8
AUXLZCEN
UPDATE
AUXL zero cross detect enable
0 = zero cross disabled
1 = zero cross enabled
Not latched
Controls simultaneous update of all Analogue Attenuation Latches
0 = Store AUXL in intermediate latch (no change to output)
1 = Store AUXL and update attenuation on all channels.
0000111
(07h)
6:0
7
AUXRA[6:0]
AUXRZCEN
1101011
(0dB)
0
Analogue Attenuation control for AUXR in 1dB steps. See Table
60.
Analogue
Attenuation
AUXR
AUXR zero cross detect enable
0 = zero cross disabled
1 = zero cross enabled
8
UPDATE
Not latched
Controls simultaneous update of all Analogue Attenuation Latches
0 = Store AUXR in intermediate latch (no change to output)
1 = Store AUXR and update attenuation on all channels.
0001000
(08h)
6:0
7
HPLA[6:0]
HPLZCEN
1101011
(0dB)
0
Analogue Attenuation control for HPHONEL in 1dB steps. See
Table 60.
Analogue
Attenuation
HPHONEL
HPHONEL zero cross detect enable
0 = zero cross disabled
1 = zero cross enabled
8
UPDATE
Not latched
Controls simultaneous update of all Analogue Attenuation Latches
0 = Store HPHONEL in intermediate latch (no change to output)
1 = Store HPHONEL and update attenuation on all channels.
0001001
(09h)
6:0
7
HPRA[6:0]
HPRZCEN
1101011
(0dB)
0
Analogue Attenuation control for HPHONER in 1dB steps. See
Table 60.
Analogue
Attenuation
HPHONER
HPHONER zero cross detect enable
0 = zero cross disabled
1 = zero cross enabled
8
UPDATE
Not latched
Controls simultaneous update of all Analogue Attenuation Latches
0 = Store HPHONER in intermediate latch (no change to output)
1 = Store HPHONER and update attenuation on all channels.
0001010
(0Ah)
6:0
7
MASTA[6:0]
MZCEN
1101011
(0dB)
0
Analogue Attenuation control for all DAC gains in 1dB steps. See
Table 60.
Analogue
Attenuation
Master zero cross detect enable
0 = zero cross disabled
Master
1 = zero cross enabled
(all channels)
8
UPDATE
Not latched
Controls simultaneous update of all Analogue Attenuation Latches
0 = Store gains in intermediate latch (no change to output)
1 = Store gains and update attenuation on all channels.
0001011
(0Bh)
7:0
8
LDA1[7:0]
UPDATE
11111111
(0dB)
Digital Attenuation control for DAC1 Left Channel (LSUMOP) in
0.5dB steps. See Table 63
Digital
Attenuation
DACL1
Not latched
Controls simultaneous update of all Attenuation Latches
0 = Store LDA1 in intermediate latch (no change to output)
1 = Store LDA1 and update attenuation on all channels
0001100
(0Ch)
7:0
8
RDA1[6:0]
UPDATE
11111111
(0dB)
Digital Attenuation control for DAC1 Right Channel (RSUMOP) in
0.5dB steps. See Table 63
Digital
Attenuation
DACR1
Not latched
Controls simultaneous update of all Attenuation Latches
0 = Store RDA1 in intermediate latch (no change to output)
1 = Store RDA1 and update attenuation on all channels.
0001101
(0Dh)
7:0
8
LDA2[7:0]
UPDATE
11111111
(0dB)
Digital Attenuation control for DAC2 Left Channel (CNTSOP) in
0.5dB steps. See Table 63
Digital
Attenuation
DACL2
Not latched
Controls simultaneous update of all Attenuation Latches
0 = Store LDA2 in intermediate latch (no change to output)
1 = Store LDA2 and update attenuation on all channels.
PP Rev 1.94 November 2004
77
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
