WM8777
Product Preview
REGISTER B15 B14 B13 B12 B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
0
0
0
0
0
REAR
REARGAIN[2:0]
000000000
R36(24h)
R37(25h)
R38(26h)
R39(27h)
R40(28h)
R41(29h)
R42(2Ah)
R43(2Bh)
R44(2Ch)
R45(2Dh)
R46(2Eh)
R47(2Fh)
R48(30h)
R49(31h)
R50(32h)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
HPSEL
CBYP
CBM
CBASS[1:0]
CLFE
CTRBL[1:0]
CLFEGAIN[2:0]
000000000
000000000
000000000
000000000
000000000
000000000
000000000
000000000
111111111
011001111
011001111
000000000
100000000
110001001
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SURRBYP SURLBYP AUXRBYP
FBASS[3:0]
AUXLBYP
UPDATE
UPDATE
UPDATE
UPDATE
UPDATEL
HPPD
ZCLEN
ZCREN
0
0
0
0
0
FTREB[3:0]
0
0
CBASS[3:0]
0
0
CTREB[3:0]
UPDATER
FTRPD
UPDATEC
FTLPD
FTLP[1:0]
CTRPD
FTRP[1:0]
CNTP[1:0]
LFEPD SURRPD SURLPD AUXRPD AUXLPD
LAG[7:0]
RAG[7:0]
ADC
ATC
0
0
0
0
0
0
TOADC
MUTER
MUTEL
AIN[5:0]
AINPD
OUTPD2
0
OUTPD1
MX2[2:0]
MX1[2:0]
MX3[2:0]
OUTPD4
OUTPD3
0
0
MX4[1:0]
110001001
100100001
101111110
R51(33h)
R52(34h)
R53(35h)
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
1
0
1
PLL_K[8:0]
PLL_K[17:9]
PLL2
ADC
PLL2
DAC
CLKOUTS
RC
PLL2TX
0
PLL_K[21:18]
FRAC_E POSTSCA
100001101
000000011
011100100
R54(36h)
R55(37h)
R56(38h)
R57(39h)
R58(3Ah)
R59(3Bh)
R60(3Ch)
R61(3Dh)
R62(3Eh)
R63(3Fh)
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
PLL_N[4:0]
PRESCALE
PLLPD
N
LE
0
0
0
0
0
0
0
0
DAC4SEL[1:0]
DAC3SEL[1:0]
PREEMPH[2:0]
CATCODE[7:0]
DAC2SEL[1:0]
DAC1SEL[1:0]
CHSTMODE[2:0]
CPY_N AUDIO_N CON/PRO 000000000
000000000
CHNUM2[1:0]
CHNUM1[1:0]
CLKACU[1:0]
SRCNUM[3:0]
FREQ[3:0]
000000000
000110001
000001011
000100010
000000010
0
0
0
MAXPAIFR
X WL
ORGSAMP[3:0]
TXPAIFRX_WL[1:0]
SAIF_B SAIF_L
SAIF_WL
[1:0]
SAIF_FMT
0
CP
RP
[1:0]
0
SAIFCLKSRC[1:0]
SMS
SAIFRATE[2:0]
ADCCL ALWAYSVA
FILLMODE
RXINSEL[1:0]
0
0
0
SPDINMODE 000000000
R64(40h)
R65(41h)
1
1
0
0
0
0
0
0
0
0
0
0
0
1
KSRC
LID
TXRXT
HRU
0
SAIFSRC[1:0]
PAIFSRC[1:0]
TXSRC[1:0]
RX2DAC
0
000010000
0
0
0
FPLL[2:0]
Reserved
Reserved
0
0
000111000
00000000
000000000
000000000
R66(42h)
R67(43h)
R68(44h)
R69(45h)
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
0
1
Reserved
Reserved
000000000
000010000
R70(46h)
R71(47h)
1
1
0
0
0
0
0
0
1
1
1
1
0
1
GPIO2OP[3:0]
GPOMODEOP[3:0]
0
0
0
GPIO1OP[3:0]
GPIO3OP[3:0]
010100010
000000000
R72(48h)
R73(49h)
1
1
0
0
0
0
1
1
0
0
0
0
0
1
MASK[7:0]
PP Rev 1.94 November 2004
74
w