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WM8777
REGISTER MAP
The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The
WM8777 can be configured using the Control Interface. All unused bits should be set to ‘0’.
REGISTER B15 B14 B13 B12 B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
X01101011
X01101011
X01101011
X01101011
X01101011
X01101011
X01101011
X01101011
X01101011
X01101011
X01101011
X11111111
X11111111
X11111111
X11111111
X11111111
X11111111
X11111111
X11111111
X11111111
000000000
100100000
000000000
000000000
000100010
000100010
111111110
000100010
000000000
001111011
000000000
100110010
000000000
010100110
000000000
000000000
UPDATE FRONTLZCEN
UPDATE FRONTRZCEN
FRONTLA[6:0]
R0(00h)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
FRONTRA[6:0]
CNTRA[6:0]
LFEA[6:0]
R1(01h)
UPDATE
UPDATE
UPDATE
UPDATE
UPDATE
UPDATE
UPDATE
UPDATE
UPDATE
UPDATE
UPDATE
UPDATE
UPDATE
UPDATE
UPDATE
UPDATE
UPDATE
UPDATE
0
CNTRZCEN
LFEZCEN
R2(02h)
R3(03h)
SURLZCEN
SURLZCEN
AUXLZCEN
AUXRZCEN
HPLZCEN
HPRZCEN
MZCEN
SURLA[6:0]
SURRA[6:0]
AUXLA[6:0]
AUXRA[6:0]
HPLA[6:0]
R4(04h)
R5(05h)
R6(06h)
R7(07h)
R8(08h)
HPRA[6:0]
R9(09h)
MASTA[6:0]
R10(0Ah)
R11(0Bh)
R12(0Ch)
R13(0Dh)
R14(0Eh)
R15(0Fh)
R16(10h)
R17(11h)
R18(12h)
R19(13h)
R20(14h)
R21(15h)
R22(16h)
R23(17h)
R24(18h)
R25(19h)
R26(1Ah)
R27(1Bh)
R28(1Ch)
R29(1Dh)
R30(1Eh)
R31(1Fh)
R32(20h)
R33(21h)
R34(22h)
R35(23h)
LDA1[7:0]
RDA1[7:0]
LDA2[7:0]
RDA2[7:0]
LDA3[7:0]
RDA3[7:0]
LDA4[7:0]
RDA4[7:0]
MASTDA[7:0]
PHASE[7:0]
PL[3:0]
TOCDAC
0
IZD
DACATC
DZCEN
RECLEN[1:0]
DZFM[3:0]
RECREN[1:0]
MUTEALL
DMUTE[3:0]
DEEMP[3:0]
0
0
MLCKOUT
SRC
PAIFRX PAIFRX
MCLKOPEN
PAIFRX_RATE[2:0]
SPDIFTXD
ADCHPD
PAIFRX_WL[1:0]
PAIFRX_FMT[1:0]
PAIFTX_RATE[2:0]
ADCPD PWDN
PAIFTX PAIFTX
PAIFTX_FMT[1:0]
BCP
LRP
PAIFRX
MS
PAIFTX_MS
DACOSR
OSCPD
SPDIFRXD
DACPD[3:0]
PAIFTX_WL
[1:0]
SYNC
ADCOSR
BCP
LRP
Reserved
MAXGAIN[2:0]
LCSEL[1:0]
LCT[3:0]
LCEN
ALCZC
0
DCY[3:0]
0
0
HLD[3:0]
ATK[3:0]
0
FDECAY
0
0
0
0
0
0
0
NGTH[2:0]
NGAT
0
0
TRANWIN[2:0]
FBYP
MAXATTEN[3:0]
FBASS[1:0] FTRBL[1:0]
FLFE FLFEGAIN[2:0]
AIN6
FBM
CNTR
CNTRGAIIN[2:0]
PP Rev 1.94 November 2004
73
w
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