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WM8777
CONTROL INTERFACE TIMING – 3-WIRE MODE
Figure 9 SPI Compatible Control Interface Input Timing
Test Conditions
DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs, ADC/DAC in Slave Mode unless otherwise
stated.
PARAMETER
SCLK rising edge to CSBrising edge
SCLK pulse cycle time
SYMBOL
tSCS
MIN
60
80
30
30
20
20
20
20
20
TYP
MAX
UNIT
ns
tSCY
ns
SCLK pulse width low
tSCL
ns
SCLK pulse width high
tSCH
ns
SDIN to SCLK set-up time
SCLK to SDIN hold time
CSB pulse width low
tDSU
ns
tDHO
tCSL
ns
ns
CSB pulse width high
tCSH
ns
CSB rising to SCLK rising
tCSS
ns
Table 14 SCLK Timing Requirements
PP Rev 1.94 November 2004
27
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
