WM8777
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CONTROL INTERFACE OPERATION
The WM8777 is controlled using a 2-wire (plus readback pin) or 3-wire (plus readback pin) SPI
compatible serial interface.
The interface configuration is determined by the state of the GPIO/MODE pin on power up. If the
GPIO/MODE pin is low while the power on reset is being applied internally, the 2-wire configuration is
selected. If GPIO/MODE is high while the power on reset is being applied internally, the 3-wire
configuration is selected - see table 11.
The control interface is 5V tolerant, meaning that the control interface input signals CSB, SCLK and
SDIN may have an input high level of 5V while DVDD is 3V. Input thresholds are determined by
DVDD.
GPIO/MODE AT
POWER UP
CONTROL
Low
2-wire
3-wire
High
Table 11 Control Interface Selection
3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE WITH ADDITIONAL
READBACK PIN
SDIN is used for the program data, SCLK is used to clock in the program data and CSB is used to
latch the program data. SDIN is sampled on the rising edge of SCLK. The 2-wire interface protocol
with readback is shown in Figure 5.
Figure 5 3 Wire SPI Compatible Interface
1. B[15:9] are Control Address Bits
2. B[8:0] are Control Data Bits
3. CSB is edge sensitive – the data is latched on the rising edge of CSB.
3-WIRE REGISTER READBACK
The read-only registers in the S/PDIF section can be read back via the SDOUT pin. To enable
readback the READEN3 bit must be set.
REGISTER ADDRESS
(4Ah)
BIT
LABEL
DEFAULT
DESCRIPTION
4
READEN3
0
3-Wire Read-back mode enable.
Read-back Control
0 = 3-Wire read-back mode
disabled
1 = 3-Wire read-back mode
enabled
5
READEN2
0
2-Wire Read-back mode enable.
0 = 2-Wire read-back mode
disabled
1 = 2-Wire read-back mode
enabled
Table 12 Readback Control Register
The 3-wire interface readback protocol is shown in Figure 6. Note that the SDOUT pin is tri-state
unless CSB is held low, therefore CSB must be held low for the duration of the read.
PP Rev 1.94 November 2004
24
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
