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WM8776_05 参数 Datasheet PDF下载

WM8776_05图片预览
型号: WM8776_05
PDF下载: 下载PDF文件 查看货源
内容描述: 24位, 192kHz立体声编解码器与5频道I / P多路复用器 [24-bit, 192kHz Stereo CODEC with 5 Channel I/P Multiplexer]
分类和应用: 解码器复用器编解码器
文件页数/大小: 57 页 / 601 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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Production Data  
WM8776  
In addition a zero cross detect circuit is provided for the output PGA volume under the control of bit 7  
(ZCEN) in the each attenuation register. When ZCEN is set the attenuation values are only updated  
when the input signal to the gain stage is close to the analogue ground level. This minimises audible  
clicks and ‘zipper’ noise as the gain values change. A timeout clock is also provided which will  
generate an update after a minimum of 131072 master clocks (= ~10.5ms with a master clock of  
12.288MHz). The timeout clock may be disabled by setting TOD.  
Left and right inputs may also be independently muted. The LRBOTH control bit allows the user to  
write the same attenuation value to both left and right volume control registers, saving on software  
writes. The ADC volume and mute also applies to the bypass signal path.  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
R14 (0Eh)  
0001110  
Attenuation  
ADCL  
7:0  
LAG[7:0]  
11001111  
(0dB)  
Attenuation data for Left channel ADC gain in 0.5dB steps. See  
Table 15.  
8
ZCLA  
0
Left channel ADC zero cross enable:  
0: Zero cross disabled  
1: Zero cross enabled  
R15 (0Fh)  
0001111  
7:0  
8
RAG[7:0]  
ZCRA  
11001111  
(0dB)  
Attenuation data for right channel ADC gain in 0.5dB steps. See  
Table 15.  
Attenuation  
ADCR  
0
0
0
0
Right channel ADC zero cross enable:  
0: Zero cross disabled  
1: Zero cross enabled  
R21 (15h)  
0010101  
8
7
6
LRBOTH  
MUTELA  
MUTERA  
Right channel input PGA controlled by left channel register  
0 : Right channel uses RAG.  
1 : Right channel uses LAG.  
Mute for left channel ADC  
0: Mute Off  
ADC Input Mux  
R21 (15h)  
0010101  
ADC Input Mux  
1: Mute on  
Mute for right channel ADC  
0: Mute Off  
1: Mute on  
ADC HIGHPASS FILTER DISABLE  
The ADC digital filters contain a digital high pass filter. This defaults to enabled and can be disabled  
using software control bit ADCHPD.  
REGISTER ADDRESS  
R11 (0Bh)  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
ADC High pass filter disable:  
0: High pass filter enabled  
1: High pass filter disabled  
8
ADCHPD  
0
0001011  
ADC Control  
PD Rev 4.0 April 2005  
33  
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