WM8776
Production Data
L/RDA[7:0]
ATTENUATION LEVEL
00(hex)
-∞ dB (mute)
01(hex)
-127dB
:
:
:
:
:
:
FE(hex)
FF(hex)
-0.5dB
0dB
Table 14 Digital Volume Control Attenuation Levels
The digital volume control also incorporates a zero cross detect circuit which detects a transition
through the zero point before updating the digital volume control with the new volume. This is
enabled by control bit DZCEN.
REGISTER ADDRESS
R7 (07h)
BIT
LABEL
DEFAULT
DESCRIPTION
0
DZCEN
0
DAC Digital Volume Zero Cross
Enable:
0000111
0: Zero cross detect disabled
1: Zero cross detect enabled
DAC Control
DAC OUTPUT PHASE
The DAC Phase control word determines whether the output of the DAC is non-inverted or inverted
REGISTER ADDRESS
R6 (06h)
BIT
LABEL
DEFAULT
DESCRIPTION
1:0
PH[1:0]
00
Bit
0
DAC
Phase
0000110
DACL
1 = invert
1 = invert
DAC Phase
1
DACR
ADC GAIN CONTROL
The ADC has an analogue input PGA and digital gain control for each stereo channel. Both the
analogue and digital gains are adjusted by the same register, LAG for the left and RAG for the right.
The analogue PGA has a range of +24dB to -21dB in 0.5dB steps. The digital gain control allows
further attenuation (after the ADC) from -21.5dB to -103dB in 0.5dB steps. Table 15 shows how the
register maps the analogue and digital gains.
LAG/RAG[7:0]
ATTENUATION
LEVEL (AT
OUTPUT)
ANALOGUE PGA
DIGITAL
ATTENUATION
00(hex)
01(hex)
:
-∞ dB (mute)
-103dB
-21dB
-21dB
:
Digital mute
-82dB
:
:
-21.5dB
-21dB
:
A4(hex)
A5(hex)
:
-21dB
-21dB
:
-0.5dB
0dB
:
CF(hex)
:
0dB
0dB
0dB
:
:
:
FE(hex)
FF(hex)
+23.5dB
+24dB
+23.5dB
+24dB
0dB
0dB
Table 15 Analogue and Digital Gain Mapping for ADC
In addition, a zero cross detect circuit is provided for the input PGA, controlled by bit 8 in each
attenuation register. This minimises audible clicks and ‘zipper’ noise by updating the gain when the
signal crosses the zero level.
PD Rev 4.0 April 2005
32
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
