Production Data
WM8776
HPLA/ HPRA[6:0]
ATTENUATION LEVEL
00(hex)
:
-∞dB (mute)
:
2F(hex)
30(hex)
:
-∞dB (mute)
-73dB
:
0dB (default)
:
79 (hex)
:
7D(hex)
7E(hex)
7F(hex)
+4dB
+5dB
+6dB
Table 13 Headphone Volume Control Attenuation Levels
In addition a zero cross detect circuit is provided for the output PGA volume under the control of bit 7
(ZCEN) in the each attenuation register. When ZCEN is set the attenuation values are only updated
when the input signal to the gain stage is close to the analogue ground level. This minimises audible
clicks and ‘zipper’ noise as the gain values change. A timeout clock is also provided which will
generate an update after a minimum of 131072 master clocks (= ~10.5ms with a master clock of
12.288MHz). The timeout clock may be disabled by setting TOD.
REGISTER ADDRESS
R7 (07h)
BIT
LABEL
DEFAULT
DESCRIPTION
3
TOD
0
DAC and ADC Analogue Zero
cross detect timeout disable
0000111
0 : Timeout enabled
1: Timeout disabled
Timeout Clock Disable
DAC DIGITAL VOLUME CONTROL
The DAC volume may also be adjusted in the digital domain using independent digital attenuation
control registers
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R3 (03h)
0000011
7:0
LDA[7:0]
11111111
(0dB)
Digital Attenuation data for Left channel DACL in 0.5dB steps. See
Table 14
Digital
Attenuation
8
UPDATED
Not latched
Controls simultaneous update of Attenuation Latches
0: Store LDA in intermediate latch (no change to output)
1: Store LDA and update attenuation on both channels
DACL
R4 (04h)
0000100
7:0
8
RDA[6:0]
11111111
(0dB)
Digital Attenuation data for Right channel DACR in 0.5dB steps. See
Table 14
Digital
Attenuation
DACR
UPDATED
Not latched
Controls simultaneous update of Attenuation Latches
0: Store RDA in intermediate latch (no change to output)
1: Store RDA and update attenuation on both channels.
R5 (05h)
0000101
7:0 MASTDA[7:0]
11111111
(0dB)
Digital Attenuation data for DAC channels in 0.5dB steps. See Table
14
Master
Digital
Attenuation
8
UPDATED
Not latched
Controls simultaneous update of Attenuation Latches
0: Store gain in intermediate latch (no change to output)
1: Store gain and update attenuation on channels.
(both channels)
PD Rev 4.0 April 2005
31
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
