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WM8776_05 参数 Datasheet PDF下载

WM8776_05图片预览
型号: WM8776_05
PDF下载: 下载PDF文件 查看货源
内容描述: 24位, 192kHz立体声编解码器与5频道I / P多路复用器 [24-bit, 192kHz Stereo CODEC with 5 Channel I/P Multiplexer]
分类和应用: 解码器复用器编解码器
文件页数/大小: 57 页 / 601 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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Production Data  
WM8776  
MAXIMUM GAIN (ALC ONLY) AND MAXIMUM ATTENUATION  
To prevent low level signals being amplified too much by the ALC, the MAXGAIN register sets the  
upper limit for the gain. This prevents low level noise being over-amplified. The MAXGAIN register  
has no effect on the limiter operation.  
The MAXATTEN register has different operation for the limiter and for the ALC. For the limiter it  
defines the maximum attenuation below the static (user programmed) gain. For the ALC, it defines  
the lower limit for the gain.  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
R16 (10h)  
0010000  
6:4  
MAXGAIN  
111  
(+24dB)  
Set maximum gain for the PGA (ALC  
only)  
111 : +24dB  
ALC Control 1  
110 : +20dB  
…..(-4dB steps)  
010 : +4dB  
001 : 0dB  
000 : 0dB  
R20 (14h)  
0010100  
3:0  
MAXATTEN  
0110  
Maximum attenuation of PGA  
Limiter  
(attenuation  
below static)  
ALC (lower PGA  
gain limit)  
Limiter Control  
1010 or lower:  
-1dB  
0011 or lower:  
-3dB  
1011 : -5dB  
….. (-4dB steps)  
1110 : -17dB  
1111 : -21dB  
0100: -4dB  
…. (-1dB steps)  
1100 or higher:  
-12dB  
HOLD TIME (ALC ONLY)  
The ALC also has a hold time, which is the time delay between the peak level detected being below  
target and the PGA gain beginning to ramp up. It can be programmed in power-of-two (2n) steps, e.g.  
2.67ms, 5.33ms, 10.67ms etc. up to 43.7ms. Alternatively, the hold time can also be set to zero. The  
hold time only applies to gain ramp-up, there is no delay before ramping the gain down when the  
signal level is above target.  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
R17 (11h)  
0010001  
3:0  
HLD[3:0]  
0000  
ALC hold time before gain is  
increased.  
0000: 0ms  
ALC Control 2  
0001: 2.67ms  
0010: 5.33ms  
… (time doubles with every step)  
1111: 43.691s  
OVERLOAD DETECTOR (ALC ONLY)  
To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes an  
overload detector. If the ADC input signal exceeds 87.5% of full scale (–1.16dB), the PGA gain is  
ramped down at the maximum attack rate (as when ATK = 0000), until the signal level falls below  
87.5% of full scale. This function is automatically enabled whenever the ALC is enabled.  
(Note: If ATK = 0000, then the overload detector makes no difference to the operation of the ALC. It  
is designed to prevent clipping when long attack times are used).  
PD Rev 4.0 April 2005  
37  
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