Production Data
WM8776
REGISTER ADDRESS
R13 (0Dh)
BIT
LABEL
DEFAULT
DESCRIPTION
6
AINPD
0
Analogue input PGA disable:
0 : Normal Mode
0001101
Powerdown Control
1: Power Down Mode
DIGITAL ATTENUATOR CONTROL MODE
Setting the ATC register bit causes the left channel attenuation settings to be applied to both left and
right channel DACs from the next audio input sample. No update to the attenuation registers is
required for ATC to take effect.
REGISTER ADDRESS
R7 (07h)
BIT
LABEL
DEFAULT
DESCRIPTION
1
ATC
0
Attenuator Control Mode:
0000111
0 : Right channel use Right
attenuation
DAC Channel Control
1: Right Channel use Left
Attenuation
INFINITE ZERO DETECT ENABLE
Setting the IZD register bit will enable the internal infinite zero detect function:
REGISTER ADDRESS
R7 (07h)
BIT
LABEL
DEFAULT
DESCRIPTION
Infinite zero Mute Enable
0 : disable infinite zero mute
1: enable infinite zero Mute
2
IZD
0
0000111
DAC Channel Control
With IZD enabled, applying 1024 consecutive zero input samples to the DAC will cause both DAC
outputs to be muted. Mute will be removed as soon as any channel receives a non-zero input.
DAC OUTPUT CONTROL
The DAC output control word determines how the left and right inputs to the audio Interface are
applied to the left and right DACs:
REGISTER ADDRESS
R7 (07h)
BIT
LABEL
DEFAULT
DESCRIPTION
7:4
PL[3:0]
1001
PL[3:0]
Left
Right
Output
Output
0000111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Mute
Left
Mute
DAC Control
Mute
Mute
Mute
Left
Right
(L+R)/2
Mute
Left
Left
Right
(L+R)/2
Mute
Left
Left
Left
Right
Right
Right
Right
(L+R)/2
(L+R)/2
(L+R)/2
(L+R)/2
Right
(L+R)/2
Mute
Left
Right
(L+R)/2
PD Rev 4.0 April 2005
29
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
