Production Data
WM8776
CONTROL INTERFACE REGISTERS
DIGITAL AUDIO INTERFACE CONTROL REGISTER
Interface format is selected via the FMT[1:0] register bits:
REGISTER ADDRESS
R10 (0Ah)
BIT
LABEL
DEFAULT
DESCRIPTION
1:0 DACFMT
[1:0]
10
Interface format Select
0001010
00 : right justified mode
01: left justified mode
10: I2S mode
DAC Interface Control
R11 (0Bh)
1:0 ADCFMT
[1:0]
10
11: DSP (early or late) mode
0001011
ADC Interface Control
In left justified, right justified or I2S modes, the LRP register bit controls the polarity of
ADCLRC/DACLRC. If this bit is set high, the expected polarity of ADCLRC/DACLRC will be the
opposite of that shown Figure 13, Figure 14, etc. Note that if this feature is used as a means of
swapping the left and right channels, a 1 sample phase difference will be introduced. In DSP modes,
the LRP register bit is used to select between early and late modes.
REGISTER ADDRESS
R10 (0Ah)
BIT
LABEL
DEFAULT
DESCRIPTION
In left/right/ I2S modes:
2
DACLRP
0
0001010
ADCLRC/DACLRC Polarity (normal)
DAC Interface Control
0 : normal ADCLRC/DACLRC
polarity
1: inverted ADCLRC/DACLRC
polarity
R11 (0Bh)
0001011
2
ADCLRP
0
In DSP mode:
ADC Interface Control
0 : Early DSP mode
1: Late DSP mode
By default, ADCLRC, DACLRC and DIN are sampled on the rising edge of ADCBCLK and DACBCLK
and should ideally change on the falling edge. Data sources that change ADCLRC/DACLRC and DIN
on the rising edge of ADCBCLK/DACBCLK can be supported by setting the BCP register bit. Setting
BCP to 1 inverts the polarity of BCLK to the inverse of that shown in Figure 13, Figure 14, etc.
REGISTER ADDRESS
R10 (0Ah)
BIT
LABEL
DEFAULT
DESCRIPTION
BCLK Polarity (DSP modes)
0 : normal BCLK polarity
1: inverted BCLK polarity
3
DACBCP
0
0001010
DAC Interface Control
R11 (0Bh)
3
ADCBCP
0
0001011
ADC Interface Control
The WL[1:0] bits are used to control the input word length.
REGISTER ADDRESS
R10 (0Ah)
BIT
LABEL
DEFAULT
DESCRIPTION
Word Length
5:4
DACWL
[1:0]
10
0001010
00 : 16 bit data
01: 20 bit data
10: 24 bit data
11: 32 bit data
DAC Interface Control
R11 (0Bh)
5:4
ADCWL
[1:0]
10
0001011
ADC Interface Control
Note: If 32-bit mode is selected in right justified mode, the WM8776 defaults to 24 bits.
In all modes, the data is signed 2's complement. The digital filters always input 24-bit data. If the
DAC is programmed to receive 16 or 20 bit data, the WM8776 pads the unused LSBs with zeros. If
the DAC is programmed into 32 bit mode, the 8 LSBs are ignored.
Note: In 24 bit I2S mode, any width of 24 bits or less is supported provided that ADCLRC/DACLRC is
high for a minimum of 24 BCLKs and low for a minimum of 24 BCLKs.
PD Rev 4.0 April 2005
25
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
