WM8776
Production Data
When operating the ADC digital interface in slave mode, to optimise the performance of the ADC it is
recommended that the ADCMCLK and ADCBCLK input signals do not have coinciding rising edges.
The ADCMCLK bit provides the option to internally invert the ADCMCLK input signal when the input
signals have coinciding rising edges.
REGISTER ADDRESS
R11(0Bh)
BIT
LABEL
DEFAULT
DESCRIPTION
ADCMCLK Polarity
0 : non-inverted
1: inverted
6
ADCMCLK
0
0001011
Interface Control
A number of options are available to control how data from the Digital Audio Interface is applied to
the DAC.
MASTER MODES
Control bit ADCMS selects between audio interface Master and Slave Modes for ADC. In ADC
Master mode ADCLRC and ADCBCLK are outputs and are generated by the WM8776. In Slave
mode ADCLRC and ADCBCLK are inputs to WM8776.
REGISTER ADDRESS
R12 (0Ch)
BIT
LABEL
DEFAULT
DESCRIPTION
9
ADCMS
0
Audio Interface Master/Slave Mode
select for ADC:
0001100
0 : Slave Mode
1: Master Mode
Interface Control
Control bit DACMS selects between audio interface Master and Slave Modes for the DAC. In DAC
Master mode DACLRC and DACBCLK are outputs and are generated by the WM8776. In Slave
mode DACLRC and DACBCLK are inputs to WM8776.
REGISTER ADDRESS
R12 (0Ch)
BIT
LABEL
DEFAULT
DESCRIPTION
8
DACMS
0
Audio Interface Master/Slave Mode
select for DAC:
0001100
0 : Slave Mode
1: Master Mode
Interface Control
MASTER MODE ADCLRC/DACLRC FREQUENCY SELECT
In ADC Master mode the WM8776 generates ADCLRC and ADCBCLK, in DAC master mode the
WM8776 generates DACLRC and DACBCLK. These clocks are derived from the master clock
(ADCMCLK or DACMCLK). The ratios of ADCMCLK to ADCLRC and DACMCLK to DACLRC are
set by ADCRATE and DACRATE respectively.
REGISTER ADDRESS
R12 (0Ch)
BIT
LABEL
DEFAULT
DESCRIPTION
2:0 ADCRATE[2:0]
010
Master Mode MCLK:ADCLRC
ratio select:
0001100
010: 256fs
011: 384fs
100: 512fs
101: 768fs
ADCLRC and DACLRC
frequency select
6:4 DACRATE[2:0]
010
Master Mode MCLK:DACLRC
ratio select:
000: 128fs
001: 192fs
010: 256fs
011: 384fs
100: 512fs
101: 768fs
PD Rev 4.0 April 2005
26
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
