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WM8773
Control bit MS selects between audio interface Master and Slave Modes. In Master mode ADCLRC
and BCLK are outputs and are generated by the WM8773. In Slave mode ADCLRC and BCLK are
inputs to WM8773.
REGISTER ADDRESS
10111
BIT
LABEL
DEFAULT
DESCRIPTION
8
MS
0
Audio Interface Master/Slave Mode
select:
Interface Control
0 : Slave Mode
1: Master Mode
MASTER MODE ADCLRC FREQUENCY SELECT
In Master mode the WM8773 generates ADCLRC and BCLK. These clocks are derived from master
clock and the ratio of MCLK to ADCLRC and are set by ADCRATE.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0111 ADCLRC frequency 2:0 ADCRATE[2:0]
select
010
Master Mode MCLK:ADCLRC
ratio select:
010: 256fs
011: 384fs
100: 512fs
101: 768fs
ADC OVERSAMPLING RATE SELECT
For ADC operation at 96kHz it is recommended that the user set the ADCOSR bit. This changes the
ADC signal processing oversample rate to 64fs.
REGISTER ADDRESS
10111
BIT
LABEL
DEFAULT
DESCRIPTION
ADC oversampling rate select
0: 128x oversampling
3
ADCOSR
0
ADC Oversampling Rate
1: 64x oversampling
MUTE MODES
Each ADC channel has an individual mute control bit, which mutes the input to the ADC. In addition
both channels may be muted by setting ADCMUTE.
REGISTER ADDRESS
11001
BIT
LABEL
DEFAULT
DESCRIPTION
ADC MUTE Left and Right
0 : Normal Operation
7
ADCMUTE
0
ADC Mute
1: mute ADC left and ADC
right
11001
5
5
MUTE
MUTE
0
0
ADC Mute select
ADC Mute Left
0 : Normal Operation
1: mute ADC left
ADC Mute select
11010
ADC Mute Right
0 : Normal Operation
1: mute ADC right
The Record outputs may be enabled by setting RECEN, where RECEN enables the RECL and
RECR outputs.
REGISTER ADDRESS
10100
BIT
LABEL
DEFAULT
DESCRIPTION
REC Output Enable
5
RECEN
0
REC Enable
0 : REC output muted
1: REC output enabled
PP Rev 1.0 June 2002
19
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
