Production Data
WM8772EFT – 32 LEAD TQFP
LEFT JUSTIFIED MODE
In left justified mode, the MSB of DIN1/2/3 is sampled by the WM8772EFT on the first rising edge of
DACBCLK following a DACLRC transition. The MSB of the ADC data is output on DOUT and
changes on the same falling edge of ADCBCLK as ADCLRC and may be sampled on the rising edge
of ADCBCLK. ADCLRC and DACLRC are high during the left samples and low during the right
samples (Figure 47).
1/fs
LEFT CHANNEL
RIGHT CHANNEL
DACLRC/
ADCLRC
DACBCLK/
ADCBCLK
DIN1/2/3/
DOUT
1
2
3
n
n-2 n-1
1
2
3
n
n-2 n-1
MSB
LSB
MSB
LSB
Figure 47 Left Justified Mode Timing Diagram
RIGHT JUSTIFIED MODE
In right justified mode, the LSB of DIN1/2/3 is sampled by the WM8772EFT on the
rising edge of DACBCLK preceding a DACLRC transition. The LSB of the ADC data is
output on DOUT and changes on the falling edge of ADCBCLK preceding a ADCLRC
transition and may be sampled on the rising edge of ADCBCLK. ADCLRC and DACLRC
are high during the left samples and low during the right samples (
Figure 48).
1/fs
LEFT CHANNEL
RIGHT CHANNEL
DACLRC/
ADCLRC
DACBCLK/
ADCBCLK
DIN1/2/3/
DOUT
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
MSB
LSB
MSB
LSB
Figure 48 Right Justified Mode Timing Diagram
PD Rev 4.2 October 2005
53
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
