Production Data
WM8772EFT – 32 LEAD TQFP
The MSB of the left channel ADC data is output on DOUT and changes on the first falling edge of
ADCBCLK following a low to high ADCLRC transition and may be sampled on the rising edge of
ADCBCLK. The right channel ADC data is contiguous with the left channel data (Figure 52)
Figure 52 DSP Mode Audio Interface - Mode A Slave, ADC
1 BCLK
1 BCLK
1/fs
ADCLRC
ADCBCLK
LEFT CHANNEL
RIGHT CHANNEL
NO VALID DATA
DOUT
1
2
n
1
2
n
n-1
n-1
MSB
LSB
Input Word Length (IWL)
Figure 53 DSP Mode Audio Interface - Mode A Master, ADC
DSP MODE B
In DSP mode B, the MSB of DAC channel 1 left data is sampled by the WM8772EFT on the first
DACBCLK rising edge following a DACLRC rising edge. DAC channel 1 right and DAC channels 2
and 3 data follow DAC channel 1 left data (Figure 54).
Figure 54 DSP Mode Audio Interface - Mode B Slave, DAC
PD Rev 4.2 October 2005
55
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
