Production Data
WM8772EFT – 32 LEAD TQFP
The signal processing for the WM8772EFT typically operates at an oversampling rate of 128fs for
both ADC and DAC. The exception to this for the DAC is for operation with a 128/192fs system clock,
e.g. for 192kHz operation, when the oversampling rate is 64fs. For ADC operation at 96kHz it is
recommended that the user set the ADCOSR bit. This changes the ADC signal processing
oversample rate to 64fs.
SAMPLING
RATE
System Clock Frequency (MHz)
128fs
192fs
256fs
384fs
512fs
768fs
(DACLRC/
ADCLRC)
32kHz
44.1kHz
48kHz
4.096
5.6448
6.144
6.144
8.467
8.192
11.2896
12.288
24.576
12.288
16.9340
18.432
36.864
16.384
22.5792
24.576
24.576
33.8688
36.864
9.216
96kHz
12.288
24.576
18.432
36.864
Unavailable Unavailable
192kHz
Unavailable Unavailable Unavailable Unavailable
Table 17 System Clock Frequencies Versus Sampling Rate
(ADC does not support 128fs and 192fs)
HARDWARE CONTROL MODES
When the MODE pin is held high, the following hardware modes of operation are available.
Note: When in hardware mode the ADC and DAC will only run in slave mode.
MUTE AND AUTOMUTE OPERATION
In both hardware and software modes, MUTE controls the selection of MUTE directly, and can be
used to enable and disable the automute function. This pin becomes an output when left floating and
indicates infinite ZERO detect (IZD) has been detected.
DESCRIPTION
0
1
Normal Operation
Mute DAC channels
Floating
Enable IZD, MUTE becomes an output to indicate when IZD occurs.
L=IZD detected, H=IZD not detected.
Table 18 Mute and Automute Control
Figure 43 shows the application and release of MUTE whilst a full amplitude sinusoid is being played
at 48kHz sampling rate. When MUTE (lower trace) is asserted, the output (upper trace) begins to
decay exponentially from the DC level of the last input sample. The output will decay towards VMID
with a time constant of approximately 64 input samples. If MUTE is applied to all channels for 1024
or more input samples the outputs will be connected directly to VMID if IZD is set. When MUTE is de-
asserted, the output will restart immediately from the current input sample.
PD Rev 4.2 October 2005
49
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
