Production Data
WM8772EFT – 32 LEAD TQFP
INPUT FORMAT SELECTION
In hardware mode, ML/I2S and MC/IWL become input controls for selection of input data format type
and input data word length for both the ADC and DAC.
ML/I2S
MC/IWL
INPUT DATA MODE
24-bit right justified
0
0
1
0
1
0
20-bit right justified
16-bit I2S
24-bit I2S
1
1
Table 19 Input Format Selection
Note:
In 24 bit I2S mode, any width of 24 bits or less is supported provided that the left/right clocks
(ADCLRC and DACLRC) are high for a minimum of 24 bit clocks (ADCBCLK and DACBCLK) and
low for a minimum of 24 bit clocks.
DE-EMPHASIS CONTROL
In hardware mode, the MD/DM pin becomes an input control for selection of de-emphasis filtering to
be applied.
MD/DM
DE-EMPHASIS
0
Off
On
1
Table 20 De-emphasis Control
DIGITAL AUDIO INTERFACE
MASTER AND SLAVE MODES
The audio interface operates in either Slave or Master mode, selectable using the DACMS and
ADCMS control bits. In both Master and Slave modes DIN1/2/3 are always inputs to the
WM8772EFT and DOUT is always an output. The default is Slave mode for ADC and DAC.
In Slave mode, ADCLRC, DACLRC and ADCBCLK, DACBCLK are inputs to the WM8772EFT
(Figure 21). DIN1/2/3, ADCLRC and DACLRC are sampled by the WM8772EFT on the rising edge of
ADCBCLK and DACBCLK respectively. ADC data is output on DOUT and changes on the falling
edge of ADCBCLK.
By setting the control bit DACBCP the polarity of DACBCLK may be reversed so that DIN1/2/3 and
DACLRC are sampled on the falling edge of DACBCLK.
By setting the control bit ADCBCP the polarity of ADCBCLK may be reversed so that ADCLRC is
sampled on the falling edge of ADCBCLK and DOUT changes on the rising edge of ADCBCLK.
ADCBCLK
ADCLRC
DSP
ENCODER/
DECODER
DACBCLK
DACLRC
DOUT
WM8772
CODEC
DIN1/2/3
3
Figure 45 Slave Mode
In Master mode, ADCLRC, DACLRC, ADCBCLK and DACBCLK are outputs from the WM8772EFT
(Figure 22). ADCLRC, DACLRC, ADCBCLK and DACBCLK are generated by the WM8772EFT.
PD Rev 4.2 October 2005
51
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
