WM8772EFT – 32 LEAD TQFP
Production Data
I2S MODE
In I2S mode, the MSB of DIN1/2/3 is sampled by the WM8772EFT on the second rising edge of
BCLK following a DACLRC transition. The MSB of the ADC data is output on DOUT and changes on
the first falling edge of BCLK following an ADCLRC transition and may be sampled on the rising edge
of BCLK. ADCLRC and DACLRC are low during the left samples and high during the right samples.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
DACLRC/
ADCLRC
DACBCLK/
ADCBCLK
1 BCLK
1 BCLK
DIN1/2/3/
DOUT
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
LSB
LSB
MSB
MSB
Figure 49 I2S Mode Timing Diagram
DSP MODE A
In DSP mode A, the MSB of DAC channel 1 left data is sampled by the WM8772EFT on the second
rising edge on DACBCLK following a DACLRC rising edge. DAC channel 1 right and DAC channels 2
and 3 data follow DAC channel 1 left data (Figure 50).
Figure 50 DSP Mode Audio Interface - Mode A Slave, DAC
1 BCLK
1 BCLK
1/fs
DACLRC
DACBCLK
CHANNEL 1
LEFT
CHANNEL 1
RIGHT
CHANNEL 2
LEFT
CHANNEL 3
RIGHT
NO VALID DATA
DIN1
1
2
n
1
2
n
1
2
n
n-1
n-1
n-1
MSB
LSB
Input Word Length (IWL)
Figure 51 DSP Mode Audio Interface - Mode A Master, DAC
PD Rev 4.2 October 2005
54
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
