WM8772EFT – 32 LEAD TQFP
Production Data
1/fs
DACLRC
DACBCLK
CHANNEL 1
LEFT
CHANNEL 1
RIGHT
CHANNEL 2
LEFT
CHANNEL 3
RIGHT
NO VALID DATA
DIN1
1
2
n
1
2
n
1
2
n
1
n-1
n-1
n-1
MSB
LSB
Input Word Length (IWL)
Figure 55 DSP Mode Audio Interface - Mode B Master, DAC
The MSB of the left channel ADC data is output on DOUT and changes on the same falling edge of
ADCBCLK as the low to high ADCLRC transition and may be sampled on the rising edge of
ADCBCLK. The right channel ADC data is contiguous with the left channel data (Figure 56).
Figure 56 DSP Mode Audio Interface - Mode A Slave, ADC
1/fs
ADCLRC
BCK
LEFT CHANNEL
RIGHT CHANNEL
NO VALID DATA
1
2
n
1
2
n
1
n-1
n-1
DOUT
MSB
LSB
Input Word Length (IWL)
Figure 57 DSP Mode Audio Interface - Mode B Master, ADC
In both DSP mode A and mode B , DACL1 is always sent first, followed immediately by DACR1 and
the data words for the other 6 channels. No BCLK edges are allowed between the data words. The
word order is DAC1 left, DAC1 right, DAC2 left, DAC2 right, DAC3 left, DAC3 right.
PD Rev 4.2 October 2005
56
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
