欢迎访问ic37.com |
会员登录 免费注册
发布采购

WM8580_07_12 参数 Datasheet PDF下载

WM8580_07_12图片预览
型号: WM8580_07_12
PDF下载: 下载PDF文件 查看货源
内容描述: 多通道编解码器S / PDIF收发器 [Multichannel CODEC with S/PDIF Transceiver]
分类和应用: 解码器编解码器光电二极管
文件页数/大小: 97 页 / 1142 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
 浏览型号WM8580_07_12的Datasheet PDF文件第53页浏览型号WM8580_07_12的Datasheet PDF文件第54页浏览型号WM8580_07_12的Datasheet PDF文件第55页浏览型号WM8580_07_12的Datasheet PDF文件第56页浏览型号WM8580_07_12的Datasheet PDF文件第58页浏览型号WM8580_07_12的Datasheet PDF文件第59页浏览型号WM8580_07_12的Datasheet PDF文件第60页浏览型号WM8580_07_12的Datasheet PDF文件第61页  
Production Data  
WM8580  
The WM8580 also transmits the preamble and VUCP bits (Validity, User Data, Channel Status and  
Parity bits).  
Validity Bit  
By default, set to 0 (to indicate valid data) with the following exceptions:  
1. TXSRC=00 (S/PDIF receiver), where Validity is the value recovered from the S/PDIF input  
stream by the S/PDIF receiver.  
2. TXVAL_OVWR=1, where Validity is the value set in registers TXVAL_SF0 and TXVAL_SF1.  
User Data  
Set to 0 as User Data configuration is not supported in the WM8580 – if TXSRC=00 (S/PDIF  
receiver) User Data is the value recovered from the S/PDIF input stream by the S/PDIF receiver.  
Channel Status  
The Channel Status bits form a 192-frame block - transmitted at one bit per sub-frame. Each sub-  
frame forms its own 192-frame block. The WM8580 is a consumer mode device and only the first 40  
bits of the block are used. All data transmitted from the WM8580 is stereo, so the channel status  
data is duplicated for both channels. The only exception to this is the channel number bits (23:20)  
which can be changed to indicate whether the channel is left or right in the stereo image. Bits within  
this block can be configured by setting the Channel Status Bit Control registers (see Table 50 to  
Table 54). If TXSRC=00 (S/PDIF receiver), the Channel Status bits are transmitted with the same  
values recovered by the receiver – unless OVWCHAN is set, in which case they are set by the  
S/PDIF transmitter channel status registers.  
Parity Bit  
This bit maintains even parity for data as a means of basic error detection. It is generated by the  
transmitter.  
For further details of all channel status bits, refer to IEC-60958-3.  
REGISTER  
ADDRESS  
BIT  
LABEL  
CHANNEL  
STATUS  
BIT  
DEFAULT  
DESCRIPTION  
R31  
SPDTXCHAN 1  
1Fh  
0
CON/PRO  
0
0
0 = Consumer Mode  
1 = Professional Mode (not supported by  
WM8580)  
1
AUDIO_N  
1
0
Linear PCM Identification  
0 = S/PDIF transmitted data is audio PCM.  
1 = S/PDIF transmitted data is not audio  
PCM.  
2
CPY_N  
2
0
0 = Transmitted data has copyright asserted.  
1 = Transmitted data has no copyright  
assertion.  
5:3  
DEEMPH[2:0]  
5:3  
000  
000 = Data from Audio interface has no pre-  
emphasis.  
001 = Data from Audio interface has pre-  
emphasis.  
010 = Reserved (Audio interface has pre-  
emphasis).  
011 = Reserved (Audio interface has pre-  
emphasis).  
All other modes are reserved and should not  
be used.  
7:6  
CHSTMODE  
[1:0]  
7:6  
00  
00 = Only valid mode for consumer  
applications.  
Table 50 S/PDIF Transmitter Channel Status Bit Control 1  
PD Rev 4.3 August 2007  
57  
w
 复制成功!