Production Data
WM8580
PHASE-LOCKED LOOPS AND S/PDIF CLOCKING (HARDWARE MODE)
In hardware mode, the user has no access to the internal clocking control registers and hence a
default configuration is loaded at reset to provide maximum functionality.
The S/PDIF receiver is enabled and hence the PLLs operate in S/PDIF receiver mode and all PLL
and S/PDIF receiver control is fully automatic. All supported S/PDIF receiver sample rates can be
used.
FREQMODE_x and POSTSCALE_x control is fully automatic to ensure that the internal MCLK is
maintained at 256fs relative to the S/PDIF received sample rate. In hardware mode, the internal
MCLK is not available at the MCLK pin (the pin defaults to an input)
In hardware mode, the OSCCLK must be 12MHz and hence the external crystal (or applied XIN
clock) must be 12MHz. No other OSCCLK frequencies are supported in hardware mode.
S/PDIF TRANSCEIVER
FEATURES
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IEC-60958-3 compatible with 32k frames/s to 96k frames/s support
Support for Reception and Transmission of S/PDIF data
Clock synthesis PLL with reference clock input and ultra-low jitter output
Input mux with support for up to four S/PDIF inputs
Register controlled Channel Status recovery and transmission
Register read-back of recovered Channel Status bits and error flags
Detection of non-audio data, sample rate, and pre-emphasised data
Programmable GPO for error flags, frame status flags and clocks
An IEC-60958-3 compatible S/PDIF transceiver is integrated into the WM8580. Operation of the
S/PDIF function may be synchronous or asynchronous to the rest of the digital audio circuits.
The receiver performs data and clock recovery, and sends recovered data either to an external
device such as a DSP (via the Digital Audio Interfaces), or if the data is audio PCM, it can route the
stereo recovered data to DAC1. The recovered clock may be routed out of the WM8580 onto a pin
for external use, and may be used to clock the internal DAC as required.
The transmitter generates S/PDIF frames where audio data may be sourced from the ADC, S/PDIF
Receiver, or the Digital Audio Interfaces.
S/PDIF FORMAT
S/PDIF is a serial, bi-phase-mark encoded data stream. An S/PDIF frame consists of two sub-
frames. Each sub-frame is made up of:
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Preamble – a synchronization pattern used to identify the start of a 192-frame block or sub-
frame
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4-bit Auxiliary Data (AUX) – ordered LSB to MSB
20-bit Audio Data (24-bit when combined with AUX) – ordered LSB to MSB
Validity Bit – a 1 indicates invalid data in that sub-frame
User Bit – over 192-frames, this forms a User Data Block,
Channel Bit – over 192-frames, this forms a Channel Status Block
Parity Bit – used to maintain even parity over the sub-frame (except the preamble)
An S/PDIF Block consists of 192 frames. Channel and User blocks are incorporated within the 192-
frame S/PDIF Block. For Consumer mode only the first 40-frames are used to make up the Channel
and User blocks. Figure 33 illustrates the S/PDIF format.
PD Rev 4.3 August 2007
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
