Production Data
WM8580
REGISTER
BIT
LABEL
CHANNEL
DEFAULT
DESCRIPTION
ADDRESS
STATUS BIT
R35
0
MAXWL
32
1
Maximum Audio sample word length
0 = 20 bits
SPDTXCHAN 5
23h
1 = 24 bits
3:1
TXWL[2:0]
35:33
101
Audio Sample Word Length.
000 = Word Length Not Indicated
TXWL[2:0]
001
MAXWL==1
20 bits
MAXWL==0
16 bits
010
22 bits
18 bits
100
23 bits
19 bits
101
24 bits
20 bits
110
21 bits
17 bits
All other combinations reserved
7:4
ORGSAMP
[3:0]
39:36
0000
Original Sampling Frequency. See S/PDIF
specification for details.
0000 = original sampling frequency not
indicated
Table 54 S/PDIF Transmitter Channel Status Bit Control 5
S/PDIF RECEIVER
INPUT SELECTOR
The S/PDIF receiver has one dedicated input, SPDIFIN1. This pin is a IEC-60958-3-compatible
comparator input by default or, if SPDIFIN1MODE is set, the pin will be a CMOS-compatible input.
There are three other pins which can be configured as either S/PDIF inputs or general purpose
outputs (GPOs). The four S/PDIF inputs are multiplexed to allow one input to go to the S/PDIF
receiver for decoding. The S/PDIF receiver can be powered down using the SPDIFRXD register bit.
PD Rev 4.3 August 2007
59
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
