WM8580
Production Data
S/PDIF RECEIVE MODE CLOCKING
In S/PDIF receive mode, the PLLA_N and PLLA_K values are automatically controlled by the
S/PDIF receiver to allow the receiver to use PLLA to lock on to and track the incoming S/PDIF data
stream. PLLB must be configured to produce a specific reference clock frequency for the S/PDIF
receiver.
The S/PDIF receiver has three clocking modes based on the incoming S/PDIF stream sample rate.
The modes are:
•
•
•
Mode 1: Incoming S/PDIF Sample Rate = 88.2kHz -1% to 96kHz +1%
Mode 2: Incoming S/PDIF Sample Rate = 44.1kHz -1% to 48kHz +1%
Mode 3: Incoming S/PDIF Sample Rate = 32kHz +/- 1%
Before the S/PDIF receiver is enabled, it is important that the PLLB_N and PLLB_K register values
(and the PRESCALE_x values as appropriate) are manually configured in a specific default state.
Note that the PRESCALE_A value must always be set to the same value as PRESCALE_B.
The specified PLLB f2 frequency that must be configured using the PLLB_N and PLLB_K register
values (and the PRESCALE_x values as appropriate) for reception of specific S/PDIF sample rates is
as follows:
•
Modes 1/2/3 (32/44.1/48/88.2/96kHz Sample Rates): PLLB f2 = 94.3104MHz
The FREQMODE_B[1:0] bits and POSTSCALE_B bit are not used in PLL S/PDIF recever mode.
The PLL register settings are configured by default to allow S/PDIF receiver operation using a 12MHz
crystal clock. The appropriate PLLB register values must be updated if any crystal clock frequency
other than 12MHz is used.
Refer to Table 48 for details of a number of recommended PLLB configurations. Many other
configurations are possible; please refer to PLL Configuration section for details regarding how to
calculate alternative settings.
OSC
CLK
(MHz)
11.2896
12
PRE-
SCALE_X
S/PDIF RECEIVER
SAMPLE RATE(S) (kHz)
F1
F2
R
PLLB_N PLLB_K
COMMENT
(MHz)
(MHz)
(Hex)
(Hex)
0
0
0
1
1
1
32 / 44.1 / 48 / 88.2 / 96 11.2896 94.3104 8.3537
8
7
7
9
7
6
16A3B3
36FD21
2B3333
Set N, K
Default Setting
Set K
32 / 44.1 / 48 / 88.2 / 96
32 / 44.1 / 48 / 88.2 / 96
32 / 44.1 / 48 / 88.2 / 96
32 / 44.1 / 48 / 88.2 / 96
32 / 44.1 / 48 / 88.2 / 96
12
94.3104 7.8592
12.288
19.2
12.288 94.3104 7.675
9.6
12
94.3104 9.824
94.3104 7.8592
94.3104 6.986
346C6A Set Prescales, N, K
36FD21 Set Prescales
3F19E5 Set Prescales, N, K
24
27
13.5
Table 48 S/PDIF Receive Mode PLLB Initial Configuration Examples
The recommended configuration sequences are as follows:
TO INITIALLY CONFIGURE THE SYSTEM FOR S/PDIF RECEIVER STARTUP:
1. Disable the PLLA and PLLB by seting the PLLAPD and PLLBPD bits
2. Write appropriate calculated values (relative to oscillator frequency) to
PRESCALE_A, PRESCALE_B, PLLB_N and PLLB_K.
3. Enable S/PDIF receiver by clearing the SPDIFRXPD and SPDIFPD bits.
4. Enable PLLA and PLLB by clearing the PLLAPD and PLLBPD bits.
PD Rev 4.3 August 2007
54
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
