Production Data
WM8580
OSC
PRE-
SCALE
_x
F1
F2
R
PLLx_N
PLLx_K
FREQ
MODE_x
[1:0]
POST-
SCALE_x
PLLxCLK
CLK
(MHz)
(MHz)
(Hex)
(Hex)
(MHz)
(MHz)
12
12
12
12
12
12
12
24
24
24
24
24
24
24
27
27
27
27
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
12
12
98.304
98.304
98.304
98.304
98.304
98.304
98.304
8.192
8.192
8.192
8.192
8.192
8.192
8.192
8
8
8
8
8
8
8
7
7
7
7
7
7
7
7
7
6
6
C49BA
C49BA
C49BA
C49BA
C49BA
C49BA
C49BA
21B089
21B089
21B089
21B089
21B089
21B089
21B089
1208A5
1208A5
2C2B24
2C2B24
00
01
01
10
10
11
11
00
01
01
10
10
11
11
00
01
00
01
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
1
1
1
24.576
24.576
12.288
12.288
6.144
12
12
12
12
8.192
12
4.096
12
90.3168 7.5264
90.3168 7.5264
90.3168 7.5264
90.3168 7.5264
90.3168 7.5264
90.3168 7.5264
90.3168 7.5264
22.5792
22.5792
11.2896
11.2896
5.6448
7.5264
3.7632
24.576
12.288
22.5792
11.2896
12
12
12
12
12
12
13.5
13.5
13.5
13.5
98.304
98.304
7.2818
7.2818
90.3168 6.6901
90.3168
6.6901
Table 46 User Mode PLL Configuration Examples
When considering settings not shown in this table, the key configuration parameters which must be
selected for optimum operation are:
•
•
•
90MHz ≤ f2 ≤ 100MHz
5 ≤ PLLx_N ≤ 13
OSCCLOCK = 10 to 14.4MHz or 16.28 to 27MHz
CLOCK OUTPUT (CLKOUT) AND MCLK OUTPUT (MCLK)
The clock output (CLKOUT) pin can be used as a clock output. This pin is intended to be used as a
clock source pin for providing the central clock reference for an audio system.
The CLKOUT clock source can be selected from OSCCLK, PLLACLK or PLLBCLK. The
control bits for the CLKOUT signal are shown in Table 47.
The MCLK pin can be configured as an input or output – the WM8580 should be powered
down when switching MCLK between an input and an output. As an output, MCLK can be
sourced from OSCCLK, PLLACLK or PLLBCLK.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R7
PLLB 4
07h
6:5
MCLKOUTSRC
00
MCLK pin output source
00 = Input – Source MCLK pin
01 = Output – Source PLLACLK
10 = Output – Source PLLBCLK
11 = Output – Source OSCCLK
CLKOUT pin source
8:7
CLKOUTSRC
11
00 = No Output (tristate)
01 = Output – Source PLLACLK
10 = Output – Source PLLBCLK
11 = Output – Source OSCCLK
Table 47 MCLK and CLKOUT Control
PD Rev 4.3 August 2007
53
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
