Production Data
WM8352
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R78 (4Eh)
Anti Pop
Control
9:8
ANTI_POP[1:0]
00
Reduces pop when VMID is enabled by setting the
speed of the S-ramp for VMID.
00 = no S-ramp (will pop)
01 = Fastest S-curve
10 = Medium S-curve
11 = Slowest S-curve
7:6
5:4
3:2
1:0
DIS_OP_LN4[1:0]
DIS_OP_LN3[1:0]
DIS_OP_OUT2[1:0]
DIS_OP_OUT1[1:0]
00
00
00
00
Sets the Discharge rate for OUT4
00 = discharge path OFF
01 = fastest discharge
10 = medium discharge
11 = slowest discharge
Sets the Discharge rate for OUT3
00 = discharge path OFF
01 = fastest discharge
10 = medium discharge
11 = slowest discharge
Sets the discharge rate for OUT2L and OUT2R
00 = discharge path OFF
01 = fastest discharge
10 = medium discharge
11 = slowest discharge
Sets the discharge rate for OUT1L and OUT1R
00 = discharge path OFF
01 = fastest discharge
10 = medium discharge
11 = slowest discharge
Register 4Eh Anti Pop Control
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R80 (50h)
Left Input
Volume
15
INL_ENA
0
0
Left input PGA enable
0 = disabled
1 = enabled
14
13
INL_MUTE
INL_ZC
Mute control for left channel input PGA:
0 = Input PGA not muted, normal operation
1 = Input PGA muted (and disconnected from the
following input record mixer).
0
Left channel input PGA zero cross enable:
0 = Update gain when gain register changes
1 = Update gain on 1st zero cross after gain register
write.
8
IN_VU
0
Input left PGA and input right PGA volume do not
update until a 1 is written to either IN_VU register bit.
7:2
INL_VOL[5:0]
01_0000 Left channel input PGA volume
000000 = -12dB
000001 = -11.25dB
.
010000 = 0dB
.
111111 = 35.25dB
Register 50h Left Input Volume
PD, February 2011, Rev 4.4
253
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
