WM8352
Production Data
REFER TO
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
Right input PGA enable
R81 (51h)
Right Input
Volume
15
INR_ENA
0
0 = disabled
1 = enabled
14
13
INR_MUTE
INR_ZC
0
0
0
Mute control for right channel input PGA:
0 = Input PGA not muted, normal operation
1 = Input PGA muted (and disconnected from the
following input record mixer).
Right channel input PGA zero cross enable:
0 = Update gain when gain register changes
1 = Update gain on 1st zero cross after gain register
write.
8
IN_VU
Input left PGA and input right PGA volume do not
update until a 1 is written to either IN_VU register bit.
7:2
INR_VOL[5:0]
01_0000 Right channel input PGA volume
000000 = -12dB
000001 = -11.25dB
.
010000 = 0dB
.
111111 = 35.25dB
Register 51h Right Input Volume
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R88 (58h)
Left Mixer
Control
15
MIXOUTL_ENA
0
Left output mixer enable.
0 = disabled
1 = enabled
12
11
2
DACR_TO_MIXOUTL
DACL_TO_MIXOUTL
IN3L_TO_MIXOUTL
INR_TO_MIXOUTL
INL_TO_MIXOUTL
0
1
0
0
0
Right DAC output to left output mixer
0 = not selected
1 = selected
Left DAC output to left output mixer
0 = not selected
1 = selected
IN3L amplifier output to left output mixer:
0 = not selected
1 = selected
1
Right input PGA output to left output mixer
0 = not selected
1 = selected
0
Left input PGA output to left output mixer
0 = not selected
1 = selected
Register 58h Left Mixer Control
PD, February 2011, Rev 4.4
254
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
