Production Data
WM8352
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R51 (33h)
DAC Digital
Volume R
15
DACR_ENA
0
Right DAC enable
0 = disabled
1 = enabled
8
DAC_VU
0
DAC left and DAC right volume do not update until a
1 is written to either DAC_VU register bit.
7:0
DACR_VOL[7:0] 1100_0000 Right DAC digital volume control:
0000_0000 = Digital mute
0000_0001 = -71.625dB
0000_0010 = -71.25dB
… (0.375dB steps)
1100_000 = 0dB
Register 33h DAC Digital Volume R
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R53 (35h)
DAC LR
Rate
11
DACLRC_ENA
0
Enables DAC LRC generation in Master
mode
0 = disabled
1 = enabled
10:0 DACLRC_RATE[10:0] 000_0100_0000 Determines the number of bit clocks per LRC
phase (when enabled)
00000000000 = invalid
...
00000000111 = invalid
00000001000 = 8 BCPS
…
11111111111 = 2047 BCPS
Register 35h DAC LR Rate
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
DAC Clock Polarity
REFER TO
R54 (36h)
DAC Clock
Control
4
DACCLK_POL
0
0 = Normal
1 = Inverted
2:0
DAC_CLKDIV[2:0]
000
DAC Sample rate divider
000 = SYSCLK / 1.0
001 = SYSCLK / 1.5
010 = SYSCLK / 2
011 = SYSCLK / 3
100 = SYSCLK / 4
101 = SYSCLK / 5.5
110 = SYSCLK / 6
111 = Reserved
Register 36h DAC Clock Control
PD, February 2011, Rev 4.4
247
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
