Production Data
WM8352
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R43 (2Bh)
FLL Control
2
15:11 FLL_RATIO [4:0]
14
CLK_VCO is divided by this integer, valid from 1 ..
31.
(0Eh)
1 recommended for high freq reference
8 recommended for low freq reference
FLL integer multiplier N for CLK_REF
9:0
FLL_N [9:0]
086h
Register 2Bh FLL Control 2
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R44 (2Ch)
FLL Control
3
15:0
FLL_K [15:0]
C226h
FLL fractional multiplier K for CLK_REF. This is only
used if FLL_FRAC is set.
Register 2Ch FLL Control 3
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R45 (2Dh)
Clock
Control 1
7
FLL_REF_FREQ
0
Low frequency reference locking
0 = High frequency reference locking (recommended
for reference clock > 48kHz)
1 = Lock frequency reference locking (recommended
for reference clock <= 48kHz)
5
FLL_FRAC
0
Fractional enable
0 = Integer Mode
1 = Fractional Mode
1 recommended in all cases
Select FLL input clock Source
00 = MCLK
1:0
FLL_CLK_SRC
[1:0]
00
01 = DACLRCLK
10 = ADCLRCLK
11 = CLK_32K_REF
Register 2Dh FLL Control 4
PD, February 2011, Rev 4.4
245
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
