Production Data
WM8352
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
Reset by state machine.
Interrupt mask.
0
IM_WKUP_GP_WAKEUP_EINT
0
0 = Do not mask interrupt.
1 = Mask interrupt.
Reset by state machine.
Register 27h Comparator Interrupt Status Mask
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R40 (28h)
Clock
15
TOCLK_ENA
0
Slow clock enable. Used for both the jack insert
detect debounce circuit and the zero cross timeout.
Control 1
0 = slow clock disabled
1 = slow clock enabled
14
TOCLK_RATE
0
Slow Clock Selection (Used for volume update
timeouts and for jack detect debounce)
0 = SYSCLK / 2^21 (Slower Response)
1 = SYSCLK / 2^19 (Faster Response)
Selects source for SYSCLK to CODEC
0 = MCLK pin
11
8
MCLK_SEL
MCLK_DIV
0
0
1 = FLL
Selects MCLK division in slave (MCLK input) mode:
0 = divide MCLK by 1
1 = divide MCLK by 2
Sets BCLK rate for Master mode
0000 = SYSCLK
7:4
BCLK_DIV[3:0]
0100
0001 = SYSCLK / 1.5
0010 = SYSCLK / 2
0011 = SYSCLK / 3
0100 = SYSCLK / 4
0101 = SYSCLK / 5.5
0101 = SYSCLK / 6
0111 = SYSCLK / 8
1000 = SYSCLK / 11
1001 = SYSCLK / 12
1010 = SYSCLK / 16
1011 = SYSCLK / 22
1100 = SYSCLK / 24
1101 = SYSCLK / 32
1110 = SYSCLK / 32
1111 = SYSCLK / 32
OPCLK Frequency (GPIO function)
000 = SYSCLK
2:0
OPCLK_DIV[2:0]
000
001 = SYSCLK / 2
010 = SYSCLK / 3
011 = SYSCLK / 4
100 = SYSCLK / 5.5
101 = SYSCLK / 6
110 = Reserved
111 = Reserved
Register 28h Clock Control 1
PD, February 2011, Rev 4.4
243
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
