WM8352
Production Data
REFER TO
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
5:4
WDOG_MODE[1:0]
00
00 = Disabled
01 = SYS_WDOG_TO interrupt on time-out
10 = WKUP_WDOG_RST interrupt and System
reset on time-out
11 = SYS_WDOG_TO interrupt on first time-out,
WKUP_WDOG_RST interrupt and System reset
on second time-out
Protected by security key. Reset by state
machine. Default held in metal mask.
2:0
WDOG_TO[2:0]
100
Watchdog timeout (seconds)
The timer is reset to this value when a
HEARTBEAT signal edge is detected or the host
writes to the watchdog control register.
000 = 0.125s
… (time doubles with each step)
101 = 4s
11x = Reserved
Protected by security key.
Register 04h System Control 2
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
0
DESCRIPTION
REFER TO
R5 (05h)
System
15
HIBERNATE
Determines what state the chip should
operate in.
Hibernate
0 = Active state
1 = Hibernate state
The register bit defaults to 0, when a reset
happens
Reset by state machine. Default held in metal
mask.
7
6
WDOG_HIB_MODE
HIB_STARTUP_SEQ
0
0
Watchdog behaviour in HIBERNATE state
0 = WDOG disabled in Hibernate
1 = WDOG controlled by WDOG_MODE in
Hibernate
Direction to take when going from Hibernate
state to the Active state.
0 = Hibernate to Active without going through
startup state
1 = Hibernate to Active goes though startup
sequence
5
REG_RESET_HIB_MODE
0
Action of the internal register reset signal
when going from Hibernate to Active.
0 = Do a register reset when leaving the
hibernate state.
1 = Do not do a register reset when leaving
the hibernate state
4
3
2
RST_HIB_MODE
IRQ_HIB_MODE
0
0
0
/RST pin state in hibernate mode:
0 = Asserted (low)
1 = Not asserted (high)
IRQ pin state in hibernate mode
0 = Normal operation
1 = Forced to indicate there is no IRQ
MEMRST_HIB_MODE
/MEMRST (Alternative GPIO function) pin
state in hibernate mode
0 = Asserted (low)
1 = Not asserted (high)
PD, February 2011, Rev 4.4
222
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
